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    • 5. 发明授权
    • High voltage insulated gate type bipolar transistor for self-isolated
smart power IC
    • 高压绝缘栅型双极晶体管,用于自隔离智能电源IC
    • US5929485A
    • 1999-07-27
    • US824318
    • 1997-03-26
    • Kenichiro Takahashi
    • Kenichiro Takahashi
    • H01L29/78H01L27/07H01L29/06H01L29/739H01L29/76H01L29/94H01L31/062
    • H01L29/0649H01L27/0716H01L29/7393
    • On a surface of one device region defined at a surface of a P-type silicon substrate, a gate electrode is formed on a thermal oxidation layer. An N-type source diffusion layer is formed at the surface of the device region, and a P-type substrate contact layer is formed adjacent the source diffusion layer. On the other hand, an N-type drain diffusion layer is formed at the surface of the other device region defined at the surface of the silicon substrate. A P-type emitter diffusion layer is formed at the surface of the center portion of the drain diffusion layer. The P-type emitter diffusion layer is confined in the drain diffusion layer. Also, an emitter terminal is connected to the emitter diffusion layer. A collector-source terminal is connected to source diffusion layer and a substrate contact layer. Also, a gate terminal is connected to the gate electrode.
    • 在限定在P型硅衬底的表面的一个器件区域的表面上,在热氧化层上形成栅电极。 在器件区域的表面形成N型源极扩散层,在源极扩散层附近形成P型衬底接触层。 另一方面,在限定在硅衬底的表面的另一个器件区域的表面上形成N型漏极扩散层。 在漏极扩散层的中心部分的表面形成P型发射极扩散层。 P型发射极扩散层被限制在漏极扩散层中。 此外,发射极端子连接到发射极扩散层。 集电极 - 源极端子连接到源极扩散层和衬底接触层。 此外,栅极端子连接到栅电极。
    • 10. 发明授权
    • Insulating gate type field effect transistor
    • 绝缘栅型场效应晶体管
    • US5744836A
    • 1998-04-28
    • US808170
    • 1997-02-28
    • Kenichiro Takahashi
    • Kenichiro Takahashi
    • H01L29/78H01L29/76H01L29/94H01L31/062
    • H01L29/7831H01L29/7836
    • There is provided a semiconductor device including a substrate having a first conductivity, a source region formed at a surface of the substrate, the source region having a second conductivity and including a lightly doped region and a heavily doped region, a drain region formed at a surface of the substrate, the drain region having a second conductivity and including a lightly doped region and a heavily doped region, an insulating film covering the substrate, a first gate electrode formed on the insulating film between the source region and the drain region, a second gate electrode formed on the insulating film above the lightly doped region of the drain region for controlling the number of carriers in the lightly doped region of the drain region, and a third gate electrode formed on the insulating film above the lightly doped region of the source region for controlling the number of carriers in the lightly doped region of the source region. In accordance with the semiconductor device, it is possible to select among a high break down voltage mode and a low resistance mode in a single semiconductor device by applying a certain voltage to the second and third gate electrodes. Thus, the semiconductor device can operate in a high break down mode while turned off in which case a high break down voltage is required, or can operate in a low resistance mode while turned on in which case a low resistance is required.
    • 提供了一种半导体器件,其包括具有第一导电性的衬底,形成在衬底的表面处的源极区域,源极区域具有第二导电性并且包括轻掺杂区域和重掺杂区域,漏极区域形成在 衬底的表面,漏极区域具有第二导电性并且包括轻掺杂区域和重掺杂区域,覆盖衬底的绝缘膜,形成在源极区域和漏极区域之间的绝缘膜上的第一栅电极, 第二栅电极,其形成在所述漏极区的所述轻掺杂区域上方的所述绝缘膜上方,用于控制所述漏极区的所述轻掺杂区域中的载流子数;以及第三栅电极,形成在所述漏极区的所述轻掺杂区域上方的所述绝缘膜上 源区域,用于控制源区域的轻掺杂区域中的载流子数。 根据半导体器件,可以通过向第二和第三栅电极施加一定电压来在单个半导体器件中选择高分压电压模式和低电阻模式。 因此,半导体器件可以在断开状态下工作,在这种情况下需要高的击穿电压,或者可以在接通时以低电阻模式工作,在这种情况下需要低电阻。