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1. 发明授权

US07559041B2 Method and apparatus for designing semiconductor integrated circuit 有权
标题翻译：半导体集成电路设计方法及设备
公开(公告)号：US07559041B2
公开(公告)日：2009-07-07
申请号：US11559731
申请日：2006-11-14
申请人： Kenichi Watanabe , Takashi Kumazaki , Akira Shoji
发明人： Kenichi Watanabe , Takashi Kumazaki , Akira Shoji
IPC分类号： G06F17/50
CPC分类号： H03K3/013 , H03K3/0375
摘要： A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit scale from increasing. A flip flop including first, second, and third latch circuits is stored as a standard cell in a cell library of a designing apparatus. The output of the second latch circuit becomes a first output signal of the flip flop. The second latch circuit provides the third latch circuit with a signal generated by latching a data signal with a clock signal. An output of the third latch circuit becomes a second output signal of the flip flop. When an error path having the possibility of a hold time violation is found, output of the flip flop in a former stage is changed from the first output to the second output in the error path.
摘要翻译：触发器装置，半导体集成电路，以及用于设计半导体集成电路的方法和装置，其防止电路规模的增加，防止定时违规。包括第一，第二和第三锁存电路的触发器作为标准单元存储在设计装置的单元库中。第二锁存电路的输出变为触发器的第一输出信号。第二锁存电路为第三锁存电路提供通过用时钟信号锁存数据信号而产生的信号。第三锁存电路的输出变为触发器的第二输出信号。当发现具有保持时间违规的可能性的错误路径时，前一级的触发器的输出在错误路径中从第一输出改变为第二输出。

2. 发明申请

US20070113213A1 FLIP FLOP FUNCTION DEVICE, SEMICONDUCTOR INTEGRATED-CIRCUIT, AND METHOD AND APPARATUS FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译： FLIP FLOP功能器件，半导体集成电路，以及设计半导体集成电路的方法和设备
公开(公告)号：US20070113213A1
公开(公告)日：2007-05-17
申请号：US11559731
申请日：2006-11-14
申请人： Kenichi Watanabe , Takashi Kumazaki , Akira Shoji
发明人： Kenichi Watanabe , Takashi Kumazaki , Akira Shoji
IPC分类号： G06F17/50 , H03K19/00 , G06F9/45 , H01L25/00
CPC分类号： H03K3/013 , H03K3/0375
摘要： A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit scale from increasing. A flip flop including first, second, and third latch circuits is stored as a standard cell in a cell library of a designing apparatus. The output of the second latch circuit becomes a first output signal of the flip flop. The second latch circuit provides the third latch circuit with a signal generated by latching a data signal with a clock signal. An output of the third latch circuit becomes a second output signal of the flip flop. When an error path having the possibility of a hold time violation is found, output of the flip flop in a former stage is changed from the first output to the second output in the error path.
摘要翻译：触发器装置，半导体集成电路，以及用于设计半导体集成电路的方法和装置，其防止电路规模的增加，防止定时违规。包括第一，第二和第三锁存电路的触发器作为标准单元存储在设计装置的单元库中。第二锁存电路的输出变为触发器的第一输出信号。第二锁存电路为第三锁存电路提供通过用时钟信号锁存数据信号而产生的信号。第三锁存电路的输出变为触发器的第二输出信号。当找到具有保持时间违规的可能性的错误路径时，前一级的触发器的输出在错误路径中从第一输出改变为第二输出。

3. 发明授权

US06346901B1 Digital-to-analog conversion circuit 失效
标题翻译：数模转换电路
公开(公告)号：US06346901B1
公开(公告)日：2002-02-12
申请号：US09470121
申请日：1999-12-22
申请人： Masami Aiura , Yuichi Nakatani , Takashi Kumazaki
发明人： Masami Aiura , Yuichi Nakatani , Takashi Kumazaki
IPC分类号： H03M180
CPC分类号： H03M1/0678 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A digital-to-analog conversion circuit including a plurality of unit current output cells (1) arranged in a matrix. Each of the current output cells (1) includes a unit current source (11) having a power supply input and a current output, and a selecting switch (12) connected to the current output and having two switching output terminals. The circuit further includes at least one ½ and/or ¼ weighted current output cell (2) disposed on a row in the matrix, and at least one ½ and/or ¼ supplementary current source (8) disposed on a desired row so that the total current consumption of the unit, weighted and supplementary current sources on each row is substantially the same. A decoder responds to a digital signal to control the switching of the selecting switches one by one as the digital signal gradually increases.
摘要翻译：一种数模转换电路，包括以矩阵排列的多个单位电流输出单元（1）。每个电流输出单元（1）包括具有电源输入和电流输出的单元电流源（11）和连接到电流输出并具有两个开关输出端子的选择开关（12）。电路还包括设置在矩阵中的行上的至少一个1/2和/或1/4加权电流输出单元（2），以及设置在期望行上的至少一个½和/或¼个辅助电流源（8），使得单位的总电流消耗量，每一行的加权和补充电流源基本相同。解码器响应于数字信号，随着数字信号逐渐增加，一个接一个地控制选择开关的切换。

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