专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5124771A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5124771A
公开(公告)日：1992-06-23
申请号：US647411
申请日：1991-01-29
申请人： Kenichi Taira , Ichiro Hase , Hiroji Kawai
发明人： Kenichi Taira , Ichiro Hase , Hiroji Kawai
IPC分类号： H01L29/68 , H01L21/331 , H01L21/334 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/76
CPC分类号： H01L29/66931 , H01L29/7606
摘要： A semiconductor device or a hot electron transistor being constructed such that an InAs base layer is sandwiched between a GaSb emitter barrier layer and a GaInAsSb-system collector barrier layer, which results in preventing hot electrons of unnecessarily high energy from being injected into the collector and an avalanche current from being generated, thereby making it possible to improve the saturation characteristics of the device.
摘要翻译：一种半导体器件或热电子晶体管被构造成使得InAs基极层夹在GaSb发射极阻挡层和GaInAsSb系集电极势垒层之间，这导致防止不必要的高能量的热电子被注入到集电极中，产生雪崩电流，从而可以提高器件的饱和特性。

2. 发明授权

US5200021A Method and apparatus for vapor deposition 失效
标题翻译：气相沉积的方法和装置
公开(公告)号：US5200021A
公开(公告)日：1993-04-06
申请号：US267635
申请日：1988-10-31
申请人： Hiroji Kawai , Syunji Imanaga , Ichiro Hase , Kunio Kaneko , Naozo Watanabe
发明人： Hiroji Kawai , Syunji Imanaga , Ichiro Hase , Kunio Kaneko , Naozo Watanabe
IPC分类号： C23C16/52
CPC分类号： C23C16/52
摘要： A method for vapor deposition includes monitoring of growth of a semiconductor layer by way of in-situ monitoring. According to the invention, in-situ monitoring is performed by irradiating a light beam onto the surface of the growing layer in a direction nearly perpendicular to the surface. Growth parameters of the layer are detected by monitoring variation of the light reflected by the surface of the layer. A growth condition in a vapor deposition chamber is feedback controlled based on the detected growth parameter.
摘要翻译：一种用于气相沉积的方法包括通过原位监测来监测半导体层的生长。根据本发明，通过在近似垂直于表面的方向上将光束照射到生长层的表面上来进行原位监测。通过监测由该层的表面反射的光的变化来检测该层的生长参数。基于检测到的生长参数反馈控制气相沉积室中的生长条件。

3. 发明授权

US4758870A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4758870A
公开(公告)日：1988-07-19
申请号：US713636
申请日：1985-03-19
申请人： Ichiro Hase , Hiroji Kawai , Shunji Imanaga , Kunio Kaneko
发明人： Ichiro Hase , Hiroji Kawai , Shunji Imanaga , Kunio Kaneko
IPC分类号： H01L29/20 , H01L29/205 , H01L29/68 , H01L29/76 , H01L29/72
CPC分类号： H01L29/205 , H01L29/7606
摘要： A III-V semiconductor device is disclosed, which includes an emitter region, an emitter barrier region having such a barrier height as to substantially restrict a thermionic emission current as compared with a tunneling current and such a barrier width as to permit the tunneling current, a base region containing indium and having higher electron affinity than said emitter region and a collector barrier region having such a barrier height as to substantially prohibit a thermally distributed electron from overflowing and such a barrier width as to substantially prohibit the tunneling current.
摘要翻译：公开了一种III-V半导体器件，其包括发射极区域，具有这样的势垒高度的发射极阻挡区域，其与隧道电流相比基本上限制热离子发射电流，并且具有允许隧穿电流的这种势垒宽度，包含铟并且具有比所述发射极区域更高的电子亲和力的基极区域和具有这样的势垒高度的集电极势垒区域，以便基本上禁止热分布电子溢出，并且这种势垒宽度基本上禁止隧穿电流。

4. 发明申请

US20070023783A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070023783A1
公开(公告)日：2007-02-01
申请号：US11459508
申请日：2006-07-24
申请人： Ichiro Hase , Ken Sawada , Masaya Uemura
发明人： Ichiro Hase , Ken Sawada , Masaya Uemura
IPC分类号： H01L31/00
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/0821
摘要： A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of semiconductor layers adjacent to each heavily doped thin sublayer.
摘要翻译：半导体器件包括发射极层：基极层; 以及集电极层，其中集电极层和发射极层各自包括具有高杂质浓度的重掺杂薄子层，并且每个重掺杂薄子层具有比与每个重掺杂薄层相邻的半导体层的杂质浓度更高的杂质浓度子层

5. 发明授权

US07067858B2 Heterojunction bipolar transistor with a base layer that contains bismuth 失效
标题翻译：具有含铋基底层的异质结双极晶体管
公开(公告)号：US07067858B2
公开(公告)日：2006-06-27
申请号：US11194600
申请日：2005-08-02
申请人： Ichiro Hase
发明人： Ichiro Hase
IPC分类号： H01L29/73
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/201 , H01L29/205 , H01L29/66318
摘要： A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III–V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n−-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.
摘要翻译：提供了具有改进特性的异质结双极晶体管（HBT）。将其中添加有Bi的III-V族化合物半导体用于基于GaAs或InP的HBT的基极层。例如，通过依次层叠由n + + -GaAs构成的子集电极层，由nO + -GaAs构成的集电极层，形成基底层由n-InGaP制成的发射极层，由n-GaAs制成的第一盖层和由n-InGaP制成的第二盖层构成的由p + 在由单晶GaAs制成的衬底1上的InGaAs。

6. 发明授权

US07462892B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07462892B2
公开(公告)日：2008-12-09
申请号：US11459508
申请日：2006-07-24
申请人： Ichiro Hase , Ken Sawada , Masaya Uemura
发明人： Ichiro Hase , Ken Sawada , Masaya Uemura
IPC分类号： H01L27/082
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/0821
摘要： A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of semiconductor layers adjacent to each heavily doped thin sublayer.
摘要翻译：半导体器件包括发射极层：基极层; 以及集电极层，其中集电极层和发射极层各自包括具有高杂质浓度的重掺杂薄子层，并且每个重掺杂薄子层具有比与每个重掺杂薄层相邻的半导体层的杂质浓度更高的杂质浓度子层

7. 发明申请

US20050263792A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050263792A1
公开(公告)日：2005-12-01
申请号：US11194600
申请日：2005-08-02
申请人： Ichiro Hase
发明人： Ichiro Hase
IPC分类号： H01L21/331 , H01L29/10 , H01L29/201 , H01L29/205 , H01L29/70 , H01L29/737 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/201 , H01L29/205 , H01L29/66318
摘要： A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n−-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.
摘要翻译：提供了具有改进特性的异质结双极晶体管（HBT）。将其中添加有Bi的III-V族化合物半导体用于基于GaAs或InP的HBT的基极层。例如，通过依次层叠由n + + -GaAs构成的子集电极层，由nO + -GaAs构成的集电极层，形成基底层由n-InGaP制成的发射极层，由n-GaAs制成的第一盖层和由n-InGaP制成的第二盖层构成的由p + 在由单晶GaAs制成的衬底1上的InGaAs。

8. 发明申请

US20050133821A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050133821A1
公开(公告)日：2005-06-23
申请号：US11050810
申请日：2005-01-27
申请人： Ichiro Hase
发明人： Ichiro Hase
IPC分类号： H01L21/331 , H01L29/10 , H01L29/201 , H01L29/205 , H01L29/70 , H01L29/737 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/201 , H01L29/205 , H01L29/66318
摘要： A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n—GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.
摘要翻译：提供了具有改进特性的异质结双极晶体管（HBT）。将其中添加有Bi的III-V族化合物半导体用于基于GaAs或InP的HBT的基极层。例如，通过依次层叠由n + GaAs构成的集电极层，由n-GaAs制成的集电极层，由p + 由n-InGaP制成的发射极层，由n-GaAs制成的第一覆盖层和由单层制成的衬底1上的由n + + -InGaAs制成的第二覆盖层晶体GaAs。

9. 发明授权

US06903387B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06903387B2
公开(公告)日：2005-06-07
申请号：US10742751
申请日：2003-12-23
申请人： Ichiro Hase
发明人： Ichiro Hase
IPC分类号： H01L21/331 , H01L29/201 , H01L29/737 , H01L31/0328
CPC分类号： H01L29/201 , H01L29/7371
摘要： A semiconductor device having a heterojunction bipolar transistor capable of suppressing the deterioration of basic transistor characteristics, such as a decline of an injection efficiency from an emitter layer to a base layer due to the rising of emitter resistance, a decline of breakdown strength between the base layer and a collector layer, or a decline of reliability due to an introduction of a defect; configured to comprise a heterojunction bipolar transistor having an emitter layer, base layer and a collector layer, wherein an electron affinity of the base layer is smaller than that of the emitter layer and that of the collector layer, an interlayer is formed at least either between the emitter layer and the base layer or between the base layer and the collector layer, and the electron affinity of the interlayer has a value between the electron affinities of the two layers sandwiching the interlayer.
摘要翻译：具有异质结双极晶体管的半导体器件能够抑制基极晶体管特性的恶化，例如由于发射极电阻的上升而从发射极层向基极层的注入效率的下降，基极之间的击穿强度的下降层和集电体层，或由于引入缺陷导致的可靠性下降; 被配置为包括具有发射极层，基极层和集电极层的异质结双极晶体管，其中所述基极层的电子亲和力小于所述发射极层的电子亲和力，并且所述集电极层的电子亲和力形成在中间层之间，发射极层和基极层之间或基极层与集电极层之间的电子亲和力，夹层中间层的两层的电子亲和力之间的值。

10. 发明申请

US20060220165A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060220165A1
公开(公告)日：2006-10-05
申请号：US10519877
申请日：2003-07-15
申请人： Ichiro Hase
发明人： Ichiro Hase
IPC分类号： H01L31/07
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/7785
摘要： There is provided a semiconductor device capable of ensuring a complete enhancement-mode operation and realizing a power transistor excellent in the low-distortion, high-efficiency performance. On a surface of a substrate (1) composed of single crystal GaAs, a second barrier layer (3) composed of AlGaAs, a channel layer (4) composed of InGaAs, a third barrier layer (12) composed of InGaP and a first barrier layer (11) composed of AlGaAs are stacked in this order, while placing in between a buffer layer (2). Relation of χ1−χ3≦0.5*(Eg3-Eg1), where χ1 is electron affinity of the first barrier layer (11), Eg1 is a band gap of the same, χ3 is electron affinity of the third barrier layer (12), and Eg3 is a band gap of the same, is satisfied between the first barrier layer (11) and the third barrier layer (12).
摘要翻译：提供了能够确保完全增强模式操作并实现低失真，高效率性能优异的功率晶体管的半导体器件。在由单晶GaAs构成的基板（1）的表面上，由AlGaAs构成的第二势垒层（3），由InGaAs构成的沟道层（4），由InGaP构成的第三势垒层（12）依次层叠由AlGaAs构成的层（11），同时放置在缓冲层（2）之间。 i chi chi chi chi chi chi chi chi chi chi chi chi chi where <<<<<< 1是第一阻挡层（11）的电子亲和力，Eg 1是与之相同的带隙，chi 3是电子亲和力在第一阻挡层（11）和第三阻挡层（12）之间，满足第三阻挡层（12）和第三阻挡层（12）和其间的带隙。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式