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1. 发明申请

US20050174857A1 Nonvolatile memory controlling method and nonvolatile memory controlling apparatus 有权
标题翻译：非易失性存储器控制方法和非易失性存储器控制装置
公开(公告)号：US20050174857A1
公开(公告)日：2005-08-11
申请号：US11047723
申请日：2005-02-02
申请人： Takahiro Fukushige , Kenichi Satori , Kenichi Nakanishi , Hideaki Bando , Junko Sasaki , Kunihiko Miura , Toshinori Nakamura , Kensuke Hatsukawa
发明人： Takahiro Fukushige , Kenichi Satori , Kenichi Nakanishi , Hideaki Bando , Junko Sasaki , Kunihiko Miura , Toshinori Nakamura , Kensuke Hatsukawa
IPC分类号： G06F12/06 , G06F12/00 , G11C5/00 , G11C16/10
CPC分类号： G11C16/10 , G11C2216/22
摘要： A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.
摘要翻译：公开了一种非易失性存储器控制方法，其连续地访问结构化以使每个存储体可独立访问的多个存储体。该方法包括以下步骤：在被访问的多个存储器组之一的繁忙周期中，向第二存储体发出访问信息以访问它; 当使用用于控制所选状态的选择信号和所述多个存储体中的任何一个的未选择状态向所述第二存储体发出访问信息时，使所述第二存储体进入选择状态; 在正在发出访问信息的同时，将忙碌周期中的存储器置于未选择状态; 以及基于在被访问的一个存储体组的忙周期中发送到第二存储体的访问信息并且与用于控制第二存储体的选择信号一起存取多个存储体。

2. 发明授权

US07836263B2 Nonvolatile memory controlling method and nonvolatile memory controlling apparatus 有权
标题翻译：非易失性存储器控制方法和非易失性存储器控制装置
公开(公告)号：US07836263B2
公开(公告)日：2010-11-16
申请号：US11047723
申请日：2005-02-02
申请人： Takahiro Fukushige , Kenichi Satori , Kenichi Nakanishi , Hideaki Bando , Junko Sasaki , Kunihiko Miura , Toshinori Nakamura , Kensuke Hatsukawa
发明人： Takahiro Fukushige , Kenichi Satori , Kenichi Nakanishi , Hideaki Bando , Junko Sasaki , Kunihiko Miura , Toshinori Nakamura , Kensuke Hatsukawa
IPC分类号： G06F13/00 , G06F13/28 , G06F12/06
CPC分类号： G11C16/10 , G11C2216/22
摘要： A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.
摘要翻译：公开了一种非易失性存储器控制方法，其连续地访问结构化以使每个存储体可独立访问的多个存储体。该方法包括以下步骤：在被访问的多个存储器组之一的繁忙周期中，向第二存储体发出访问信息以访问它; 当使用用于控制所选状态的选择信号和所述多个存储体中的任何一个的未选择状态向所述第二存储体发出访问信息时，使所述第二存储体进入选择状态; 在正在发出访问信息的同时，将忙碌周期中的存储器置于未选择状态; 以及基于在被访问的一个存储体组的忙周期中发送到第二存储体的访问信息并且与用于控制第二存储体的选择信号一起存取多个存储体。

3. 发明授权

US07530005B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US07530005B2
公开(公告)日：2009-05-05
申请号：US11222128
申请日：2005-09-08
申请人： Kenichi Satori , Kenichi Nakanishi , Hideaki Bando , Takahiro Fukushige
发明人： Kenichi Satori , Kenichi Nakanishi , Hideaki Bando , Takahiro Fukushige
IPC分类号： G11C29/00
CPC分类号： G11B20/18 , G06F11/1068 , G11C16/28
摘要： The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only “1s”, the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof “0”, followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.
摘要翻译：本发明是为了实现能够从擦除处理应用区域正常地读出数据的存储装置。在半导体存储装置1中，当对存储部分2中的擦除处理应用区域进行数据读取处理以读出仅包含“1”的擦除状态实际数据Ddr和擦除状态奇偶校验数据Ddp时，擦除 - 状态实际数据Ddr和擦除状态奇偶校验数据Ddp由第三数据反相电路13反相，使其全部值为“0”，随后执行错误检测处理。利用上述配置，可以防止在错误检测处理中检测到错误。

4. 发明申请

US20060077583A1 Storage device 有权
公开(公告)号：US20060077583A1
公开(公告)日：2006-04-13
申请号：US11222128
申请日：2005-09-08
申请人： Kenichi Satori , Kenichi Nakanishi , Hideaki Bando , Takahiro Fukushige
发明人： Kenichi Satori , Kenichi Nakanishi , Hideaki Bando , Takahiro Fukushige
IPC分类号： G11B5/09
CPC分类号： G11B20/18 , G06F11/1068 , G11C16/28
摘要： The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only “1s”, the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof “0”, followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.

5. 发明申请

US20060184758A1 Storage device 失效
标题翻译：储存设备
公开(公告)号：US20060184758A1
公开(公告)日：2006-08-17
申请号：US11329843
申请日：2006-01-11
申请人： Kenichi Satori , Keiichi Tsutsui , Kenichi Nakanishi , Hideaki Bando , Hideaki Okubo , Yoshitaka Aoki , Tamaki Konno
发明人： Kenichi Satori , Keiichi Tsutsui , Kenichi Nakanishi , Hideaki Bando , Hideaki Okubo , Yoshitaka Aoki , Tamaki Konno
IPC分类号： G06F13/28
CPC分类号： G06F3/0656 , G06F3/0613 , G06F3/0679 , G11C7/22
摘要： A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination device to which the storage device is connectable and a data reading process for reading data requested by the connection destination device.
摘要翻译：存储装置包括存储数据的多个存储器; 以及控制所述存储器的控制器，所述控制器在多个存储器中并行执行所述数量，所述数量由所提供的指定信号指定，所述数据写入处理用于写入从所述存储设备所连接的连接目的地设备提供的数据可连接和用于读取由连接目的地设备请求的数据的数据读取过程。

6. 发明授权

US07325104B2 Storage device using interleaved memories to control power consumption 失效
标题翻译：存储设备使用交错存储器来控制功耗
公开(公告)号：US07325104B2
公开(公告)日：2008-01-29
申请号：US11329843
申请日：2006-01-11
申请人： Kenichi Satori , Keiichi Tsutsui , Kenichi Nakanishi , Hideaki Bando , Hideaki Okubo , Yoshitaka Aoki , Tamaki Konno
发明人： Kenichi Satori , Keiichi Tsutsui , Kenichi Nakanishi , Hideaki Bando , Hideaki Okubo , Yoshitaka Aoki , Tamaki Konno
IPC分类号： G06F13/00
CPC分类号： G06F3/0656 , G06F3/0613 , G06F3/0679 , G11C7/22
摘要： A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination device to which the storage device is connectable and a data reading process for reading data requested by the connection destination device.
摘要翻译：存储装置包括存储数据的多个存储器; 以及控制所述存储器的控制器，所述控制器在多个存储器中并行执行所述数量，所述数量由所提供的指定信号指定，所述数据写入处理用于写入从所述存储设备所连接的连接目的地设备提供的数据可连接和用于读取由连接目的地设备请求的数据的数据读取过程。

7. 发明申请

US20080016291A1 Information storage apparatus, information transfer method, information transfer system, program, and storage medium 有权
标题翻译：信息存储装置，信息传递方法，信息传送系统，程序和存储介质
公开(公告)号：US20080016291A1
公开(公告)日：2008-01-17
申请号：US11820822
申请日：2007-06-21
申请人： Naohiro Adachi , Kenichi Satori , Kenichi Nakanishi , Tamaki Konno , Junko Nagata
发明人： Naohiro Adachi , Kenichi Satori , Kenichi Nakanishi , Tamaki Konno , Junko Nagata
IPC分类号： G06F12/02
CPC分类号： G06F3/0661 , G06F3/061 , G06F3/0673
摘要： An information storage apparatus transmits or receives information to or from another information processing apparatus in one of a plurality of data transfer modes. The information storage apparatus includes first storage means for storing the information; information transmission/reception control means for controlling transmission or reception of the information between the first storage means and second storage means contained in the other information processing apparatus; command analysis means for analyzing a command supplied from the other information processing apparatus to determine which of the plurality of data transfer modes should be applied; and configuration means for configuring the information transmission/reception control means based on a result of determination of the data transfer mode by the command analysis means.
摘要翻译：信息存储装置以多种数据传送模式之一向另一信息处理装置发送信息或从另一信息处理装置接收信息。信息存储装置包括用于存储信息的第一存储装置; 信息发送/接收控制装置，用于控制第一存储装置和其它信息处理装置中包含的第二存储装置之间的信息的发送或接收; 命令分析装置，用于分析从其他信息处理装置提供的命令，以确定应应用多个数据传输模式中的哪一个; 以及配置装置，用于基于由命令分析装置确定数据传输模式的结果来配置信息发送/接收控制装置。

8. 发明授权

US08468273B2 Information storage apparatus, information transfer method, information transfer system, program, and storage medium 有权
标题翻译：信息存储装置，信息传递方法，信息传送系统，程序和存储介质
公开(公告)号：US08468273B2
公开(公告)日：2013-06-18
申请号：US11820822
申请日：2007-06-21
申请人： Naohiro Adachi , Kenichi Satori , Kenichi Nakanishi , Tamaki Konno , Junko Nagata
发明人： Naohiro Adachi , Kenichi Satori , Kenichi Nakanishi , Tamaki Konno , Junko Nagata
IPC分类号： G06F3/00
CPC分类号： G06F3/0661 , G06F3/061 , G06F3/0673
摘要： An information storage apparatus transmits or receives information to or from another information processing apparatus in one of a plurality of data transfer modes. The information storage apparatus includes first storage means for storing the information; information transmission/reception control means for controlling transmission or reception of the information between the first storage means and second storage means contained in the other information processing apparatus; command analysis means for analyzing a command supplied from the other information processing apparatus to determine which of the plurality of data transfer modes should be applied; and configuration means for configuring the information transmission/reception control means based on a result of determination of the data transfer mode by the command analysis means.
摘要翻译：信息存储装置以多种数据传送模式之一向另一信息处理装置发送信息或从另一信息处理装置接收信息。信息存储装置包括用于存储信息的第一存储装置; 信息发送/接收控制装置，用于控制第一存储装置和其它信息处理装置中包含的第二存储装置之间的信息的发送或接收; 命令分析装置，用于分析从其他信息处理装置提供的命令，以确定应应用多个数据传输模式中的哪一个; 以及配置装置，用于基于由命令分析装置确定数据传输模式的结果来配置信息发送/接收控制装置。

9. 发明申请

US20120047290A1 CARD TYPE PERIPHERAL APPARATUS AND HOST APPARATUS 有权
标题翻译：卡类型外围设备和主机设备
公开(公告)号：US20120047290A1
公开(公告)日：2012-02-23
申请号：US13283876
申请日：2011-10-28
申请人： Tamaki Konno , Kenichi Satori , Junko Nagata , Noriyuki Hosoe , Naohiro Adachi , Kenichi Nakanishi
发明人： Tamaki Konno , Kenichi Satori , Junko Nagata , Noriyuki Hosoe , Naohiro Adachi , Kenichi Nakanishi
IPC分类号： G06F3/00
CPC分类号： G06F13/4221
摘要： A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.
摘要翻译：一种与主机装置连接的卡型外围装置，用于根据具体协议进行通信。卡型外围设备包括多个配置寄存器，其被配置为可被主机设备访问并且被设置为具有不同的设置信息。多个配置寄存器中的至少一个是特殊寄存器，其被配置为设置有由制造或销售卡类型外围设备的供应商任意选择并固定地建立的数据。特殊寄存器设置有用于区分特定协议的协议标识信息。

10. 发明授权

US08073987B2 PCI express card type peripheral apparatus and host apparatus for accessing parts of protocol ID information stored in storage unit one part after another 有权
标题翻译： PCI Express卡型外围装置和主机装置，用于一个接一个地存储存储在存储单元中的协议ID信息的一部分
公开(公告)号：US08073987B2
公开(公告)日：2011-12-06
申请号：US12949037
申请日：2010-11-18
申请人： Tamaki Konno , Kenichi Satori , Junko Nagata , Noriyuki Hosoe , Naohiro Adachi , Kenichi Nakanishi
发明人： Tamaki Konno , Kenichi Satori , Junko Nagata , Noriyuki Hosoe , Naohiro Adachi , Kenichi Nakanishi
IPC分类号： G06F3/00
CPC分类号： G06F13/4221
摘要： A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.
摘要翻译：一种与主机装置连接的卡型外围装置，用于根据具体协议进行通信。卡型外围设备包括多个配置寄存器，其被配置为可被主机设备访问并且被设置为具有不同的设置信息。多个配置寄存器中的至少一个是特殊寄存器，其被配置为设置有由制造或销售卡类型外围设备的供应商任意选择并固定地建立的数据。特殊寄存器设置有用于区分特定协议的协议标识信息。

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