专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080244329A1 APPARATUS DIAGNOSING METHOD, APPARATUS DIAGNOSIS MODULE, AND APPARATUS MOUNTED WITH APPARATUS DIAGNOSIS MODULE 审中-公开
标题翻译：装置诊断方法，装置诊断模块和装置与装置诊断模块
公开(公告)号：US20080244329A1
公开(公告)日：2008-10-02
申请号：US12044003
申请日：2008-03-07
申请人： Kenichi SHINBO , Tadanobu Toba , Katsunori Hirano
发明人： Kenichi SHINBO , Tadanobu Toba , Katsunori Hirano
IPC分类号： G06F11/00
CPC分类号： G06F11/24 , G01P21/00
摘要： An apparatus diagnosing method is a method in which, in an apparatus including a control apparatus and a control board for controlling the control apparatus, on the controlling board, an error occurrence at the control apparatus and the control board is detected, an error signal is outputted, sensor data outputted from a sensor acquiring data about operation environments of the control apparatus and the control board is collected, and an environmental factor causing a failure or an error of the control apparatus and the control board is specified based upon the error signal and the sensor data, and the sensor data is collected in association with the error signal when the sensor data is collected.
摘要翻译：一种装置诊断方法是一种方法，在包括控制装置和用于控制控制装置的控制板的装置中，在控制板上检测到控制装置和控制板上的错误发生，误差信号为输出从传感器输出的传感器数据，获取关于控制装置和控制板的操作环境的数据，并且基于误差信号指定导致控制装置和控制板的故障或错误的环境因素，当传感器数据被收集时，传感器数据和传感器数据与误差信号相关联地被收集。

2. 发明授权

US07870428B2 Method of diagnosing circuit board, circuit board, and CPU unit 有权
标题翻译：诊断电路板，电路板和CPU单元的方法
公开(公告)号：US07870428B2
公开(公告)日：2011-01-11
申请号：US11764833
申请日：2007-06-19
申请人： Katsunori Hirano , Tadanobu Toba , Yuji Sonoda
发明人： Katsunori Hirano , Tadanobu Toba , Yuji Sonoda
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： In a circuit board on which a plurality of CPUs are mounted, the CPUs comprises: monitor units for outputting task statuses of the respective CPUs; and a diagnosis circuit connected to the plurality of CPUs, comparing and judging combinations of the task statuses of the plurality of CPUs based on information on task statuses outputted from the monitor units, and detecting false operations and failures of the circuit board.
摘要翻译：在其上安装有多个CPU的电路板中，CPU包括：用于输出各个CPU的任务状态的监视单元; 以及连接到所述多个CPU的诊断电路，基于从所述监视器单元输出的任务状态的信息，比较和判断所述多个CPU的任务状态的组合，以及检测所述电路板的错误操作和故障。

3. 发明授权

US07137055B2 Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory 有权
标题翻译：半导体测试设备，半导体测试方法，半导体制造方法和半导体存储器
公开(公告)号：US07137055B2
公开(公告)日：2006-11-14
申请号：US11012355
申请日：2004-12-16
申请人： Katsunori Hirano , Shuji Kikuchi , Yuji Sonoda , Wen Li , Tadanobu Toba , Takashi Kanesaka , Masayuki Takahashi
发明人： Katsunori Hirano , Shuji Kikuchi , Yuji Sonoda , Wen Li , Tadanobu Toba , Takashi Kanesaka , Masayuki Takahashi
IPC分类号： G06F11/00
CPC分类号： G11C29/56004 , G01R31/31935 , G11C29/56
摘要： Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.
摘要翻译：根据本发明的半导体测试设备包括：算法模式发生器，用于产生用于测试被测存储器的测试模式并将该模式应用于被测存储器; 用于比较来自被测存储器的响应信号和来自tho算法模式发生器的期望值的比较器; 当由比较器比较的结果失败时，存储被测存储器的地址（故障地址）的故障地址获取部分; 用于分析故障地址并计算要修复的地址（修复地址）的故障地址分析部分; 以及用于将要修复的地址插入测试图案并将该地址应用于被测存储器的冗余处理的循环模式发生器，使得即使当半导体存储器的容量增加时，其制造成品率通过测试提高包装后的存储器和通过执行有缺陷的冗余处理。

4. 发明申请

US20090072138A1 Test Apparatus 有权
标题翻译：测试仪器
公开(公告)号：US20090072138A1
公开(公告)日：2009-03-19
申请号：US12173038
申请日：2008-07-15
申请人： Katsunori HIRANO , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
发明人： Katsunori HIRANO , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
IPC分类号： G01N23/00
CPC分类号： G01N23/2251 , H01J2237/221 , H01J2237/2817
摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.
摘要翻译：用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。用任意方向的电子束扫描样品中要测试的区域。作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够执行高速扫描控制的具有多种扫描类型的测试装置。

5. 发明申请

US20110180708A1 Test Apparatus 有权
标题翻译：测试仪器
公开(公告)号：US20110180708A1
公开(公告)日：2011-07-28
申请号：US13081875
申请日：2011-04-07
申请人： Katsunori Hirano , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
发明人： Katsunori Hirano , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
IPC分类号： H01J37/28
CPC分类号： G01N23/2251 , H01J2237/221 , H01J2237/2817
摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.
摘要翻译：用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。用任意方向的电子束扫描样品中要测试的区域。作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够执行高速扫描控制的具有多种扫描类型的测试装置。

6. 发明授权

US08304726B2 Test apparatus 有权
标题翻译：测试仪器
公开(公告)号：US08304726B2
公开(公告)日：2012-11-06
申请号：US13081875
申请日：2011-04-07
申请人： Katsunori Hirano , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
发明人： Katsunori Hirano , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
IPC分类号： H01J37/304
CPC分类号： G01N23/2251 , H01J2237/221 , H01J2237/2817
摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.
摘要翻译：用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。用任意方向的电子束扫描样品中要测试的区域。作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够执行高速扫描控制的具有多种扫描类型的测试装置。

7. 发明申请

US20110279143A1 SEMICONDUCTOR WAFER TESTING APPARATUS 审中-公开
标题翻译：半导体测试仪器
公开(公告)号：US20110279143A1
公开(公告)日：2011-11-17
申请号：US13133970
申请日：2009-09-18
申请人： Tadanobu Toba , Katsunori Hirano , Norio Sato , Masahiro Ohashi
发明人： Tadanobu Toba , Katsunori Hirano , Norio Sato , Masahiro Ohashi
IPC分类号： G01R31/26
CPC分类号： G01B15/00 , G01R31/307 , H01L22/12
摘要： Disclosed is a semiconductor wafer testing apparatus that resolves the following problems which arise when semiconductor wafers become larger: (1) complexity of stage acceleration/deceleration control; (2) throughput reduction; and (3) increased vibration of the stage support platform during the stage inversion operation (deterioration in resolution). In the semiconductor wafer testing apparatus for resolving these problems, a wafer is rotated, an electro beam is irradiated onto the rotating wafer from a scanning electron microscope, and secondary electrons emitted from the wafer are detected. The detected secondary electrons are A/D converted by an image processing unit, realigned by an image data realignment unit, and then image-processed for display. As a result, image information of all dies of a wafer can be acquired without a large amount of movement of the stage in the X and the Y directions.
摘要翻译：公开了一种半导体晶片测试装置，其解决了当半导体晶片变大时出现的以下问题：（1）阶段加速/减速控制的复杂性; （2）吞吐量减少; 和（3）在舞台反转操作期间舞台支撑平台的振动增加（分辨率降低）。在用于解决这些问题的半导体晶片测试装置中，旋转晶片，电子束从扫描电子显微镜照射到旋转晶片上，并且检测从晶片发射的二次电子。所检测的二次电子被图像处理单元进行A / D转换，由图像数据重新对准单元重新对准，然后进行图像处理以进行显示。结果，可以获得晶片的所有管芯的图像信息，而不需要在X和Y方向上的台的大量移动。

8. 发明授权

US07952072B2 Test apparatus 有权
标题翻译：测试仪器
公开(公告)号：US07952072B2
公开(公告)日：2011-05-31
申请号：US12173038
申请日：2008-07-15
申请人： Katsunori Hirano , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
发明人： Katsunori Hirano , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
IPC分类号： H01J37/304
CPC分类号： G01N23/2251 , H01J2237/221 , H01J2237/2817
摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.
摘要翻译：用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。用任意方向的电子束扫描样品中要测试的区域。作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够进行高速扫描控制的具有多种扫描类型的测试装置。

9. 发明申请

US20080010533A1 METHOD OF DIAGNOSING CIRCUIT BOARD, CIRCUIT BOARD, AND CPU UNIT 有权
标题翻译：诊断电路板，电路板和CPU单元的方法
公开(公告)号：US20080010533A1
公开(公告)日：2008-01-10
申请号：US11764833
申请日：2007-06-19
申请人： KATSUNORI HIRANO , Tadanobu Toba , Yuji Sonoda
发明人： KATSUNORI HIRANO , Tadanobu Toba , Yuji Sonoda
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： In a circuit board on which a plurality of CPUs are mounted, the CPUs comprises: monitor units for outputting task statuses of the respective CPUs; and a diagnosis circuit connected to the plurality of CPUs, comparing and judging combinations of the task statuses of the plurality of CPUs based on information on task statuses outputted from the monitor units, and detecting false operations and failures of the circuit board.
摘要翻译：在其上安装有多个CPU的电路板中，CPU包括：用于输出各个CPU的任务状态的监视单元; 以及连接到所述多个CPU的诊断电路，基于从所述监视器单元输出的任务状态的信息，比较和判断所述多个CPU的任务状态的组合，以及检测所述电路板的错误操作和故障。

10. 发明授权

US07114110B2 Semiconductor device, and the method of testing or making of the semiconductor device 失效
公开(公告)号：US07114110B2
公开(公告)日：2006-09-26
申请号：US10413135
申请日：2003-04-15
申请人： Shuji Kikuchi , Tadanobu Toba , Katsunori Hirano , Yuji Sonoda , Takeshi Wada
发明人： Shuji Kikuchi , Tadanobu Toba , Katsunori Hirano , Yuji Sonoda , Takeshi Wada
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318505 , G01R31/31813 , G01R31/318511 , G01R31/31928 , G01R31/31932
摘要： A signature circuit, i.e., a random-number generating circuit, is provided in a memory test apparatus. Also, a signature circuit is provided in each of devices-under-test. This configuration allows the large number of semiconductor integrated-circuit devices to be tested at one time with a high efficiency. This condition realizes a tremendous reduction in the test cost.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式