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1. 发明授权

US6018559A Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time 失效
公开(公告)号：US6018559A
公开(公告)日：2000-01-25
申请号：US768098
申请日：1996-12-16
申请人： Kengo Azegami , Koichi Yamashita
发明人： Kengo Azegami , Koichi Yamashita
IPC分类号： G11C19/00 , G11C19/28 , H03K19/177
CPC分类号： G11C19/28 , G11C19/00
摘要： A shift register having a plurality of circuit cells successively connected in a chain formation is proposed. Each of the circuit cells includes a first inversion gate, a first transmission gate, connected to an output of the first inversion gate, being switched by a clock, and a second inversion gate connected to an output of the first transmission gate. The circuit cell further includes a first P-channel transistor, connected between an output of the second inversion gate and an input of the first inversion gate, being switched by the clock, a second transmission gate, connected to the output of the second inversion gate, being switched by an inversion clock, and a second P-channel transistor, connected to the output of the first transmission gate, being switched by the inversion clock. In the shift register, the plurality of circuit cells are successively connected such that the input of the first inversion gate of the circuit cell is connected to an output of a second transmission gate of a former-stage circuit cell, and the output of the first inversion gate of the circuit cell is connected to an output of a second P-channel transistor of the former-stage circuit cell.

2. 发明授权

US06404224B1 Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time 失效
标题翻译：链接移位寄存器和可编程逻辑电路，其逻辑功能可实时更改
公开(公告)号：US06404224B1
公开(公告)日：2002-06-11
申请号：US09338596
申请日：1999-06-23
申请人： Kengo Azegami , Koichi Yamashita
发明人： Kengo Azegami , Koichi Yamashita
IPC分类号： H03K19173
CPC分类号： G11C19/28 , G11C19/00
摘要： A shift register having a plurality of circuit cells successively connected in a chain formation is proposed. Each of the circuit cells includes a first inversion gate, a first transmission gate, connected to an output of the first inversion gate, being switched by a clock, and a second inversion gate connected to an output of the first transmission gate. The circuit cell further includes a first P-channel transistor, connected between an output of the second inversion gate and an input of the first inversion gate, being switched by the clock, a second transmission gate, connected to the output of the second inversion gate, being switched by an inversion clock, and a second P-channel transistor, connected to the output of the first transmission gate, being switched by the inversion clock. In the shift register, the plurality of circuit cells are successively connected such that the input of the first inversion gate of the circuit cell is connected to an output of a second transmission gate of a former-stage circuit cell, and the output of the first inversion gate of the circuit cell is connected to an output of a second P-channel transistor of the former-stage circuit cell.
摘要翻译：提出了一种具有连续地连接在链形中的多个电路单元的移位寄存器。每个电路单元包括连接到第一反相门的输出端的第一反相门，第一输入门，被时钟切换，以及连接到第一传输门的输出的第二反相门。电路单元还包括第一P沟道晶体管，连接在第二反向栅极的输出端和第一反向栅极的输入端之间，被时钟切换;第二传输门极，连接到第二反向栅极的输出端被反转时钟切换，并且连接到第一传输门的输出的第二P沟道晶体管被反转时钟切换。在移位寄存器中，多个电路单元被连续地连接，使得电路单元的第一反向门的输入连接到前级电路单元的第二传输门的输出端，并且第一电路单元的反相栅极连接到前级电路单元的第二P沟道晶体管的输出。

3. 发明授权

US5442246A Programmable logic circuit 失效
标题翻译：可编程逻辑电路
公开(公告)号：US5442246A
公开(公告)日：1995-08-15
申请号：US128223
申请日：1993-09-29
申请人： Kengo Azegami , Koichi Yamashita
发明人： Kengo Azegami , Koichi Yamashita
IPC分类号： H03K19/177
CPC分类号： H03K19/17704
摘要： A programmable logic circuit is provided with a plurality of logic cells including specific logic cells, at least two sub blocks, included in the specific logic cell, respectively having two or more inputs and one or more outputs and having only a predetermined combinational logic function by itself, and a switching circuit, included in the specific logic cell, and capable of independently connecting a path between the input and output of each sub block. An arbitrary combinational logic function and an arbitrary sequential logic function are realized by programming ON/OFF states of the switching circuit.
摘要翻译：可编程逻辑电路具有包括特定逻辑单元的多个逻辑单元，包括在特定逻辑单元中的至少两个子块，分别具有两个或更多个输入和一个或多个输出，并且仅具有预定的组合逻辑功能，本身以及包含在特定逻辑单元中的开关电路，并且能够独立地连接每个子块的输入和输出之间的路径。通过编程开关电路的ON / OFF状态来实现任意组合逻辑功能和任意顺序逻辑功能。

4. 发明授权

US06323678B1 Integrated circuit device with programmable junctions and method of designing such integrated circuit device 失效
标题翻译：具有可编程结的集成电路器件和设计这种集成电路器件的方法
公开(公告)号：US06323678B1
公开(公告)日：2001-11-27
申请号：US08909085
申请日：1997-08-14
申请人： Kengo Azegami
发明人： Kengo Azegami
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： According to the present invention, there is also provided a field gate array comprising a matrix of logic cells each having n input terminals, a plurality of intercell buses disposed between the logic cells and each having a plurality of intercell signal lines, and programmable junctions disposed around the logic cells and each including the intercell signal lines, n input terminal lines intersecting with the intercell signal lines and connected to the input terminals, and programmable switches disposed at intersections between the intercell signal lines and the input terminal lines, the switches being placed at positions for connecting n of the first signal lines to at least one combination of the n input terminal lines and for connecting optional m (m
摘要翻译：根据本发明，还提供了一种场门阵列，其包括每个具有n个输入端的逻辑单元矩阵，多个单元间总线设置在逻辑单元之间，每个具有多个单元间信号线，并且可编程接点被布置在逻辑单元周围并且每个包括单元间信号线，与单元间信号线相交并连接到输入端的n个输入端线以及设置在单元间信号线和输入端线之间的交叉点处的可编程开关，开关被放置用于将n个第一信号线连接到n个输入端线的至少一个组合的位置，并用于将任选的m（m

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