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1. 发明申请

US20140024138A1 METHOD FOR ETCHING METAL LAYER AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：用于蚀刻金属层的方法和使用其制造半导体器件的方法
公开(公告)号：US20140024138A1
公开(公告)日：2014-01-23
申请号：US13941071
申请日：2013-07-12
申请人： Hyungjoon Kwon , Ken Tokashiki , Jongchul Park
发明人： Hyungjoon Kwon , Ken Tokashiki , Jongchul Park
IPC分类号： H01L21/3065 , H01L43/12
CPC分类号： H01L21/3065 , C23F4/00 , H01L21/32136 , H01L43/12
摘要： The inventive concepts disclosed herein include, for instance, methods for etching a metal layer and methods for manufacturing a semiconductor device using the etched metal layer. A wafer including a metal layer and a mask layer on the metal layer may be loaded into a process chamber. An etching gas may be supplied into the process chamber to etch the metal layer exposed by the mask layer. After the etching process, the mask layer may be removed. The etching gas can include phosphorus (P) and fluorine (F). An RF power may be constantly or selectively supplied to the process chamber, or different levels of RF power can be selectively supplied. An etching gas can be supplied to the process chamber when the RF power is off or at a lower level. A surface activation gas can be supplied when the RF power is on or at a higher level.
摘要翻译：本文公开的发明构思包括例如蚀刻金属层的方法和使用蚀刻金属层制造半导体器件的方法。在金属层上包括金属层和掩模层的晶片可以被加载到处理室中。可以将蚀刻气体供应到处理室中以蚀刻由掩模层暴露的金属层。在蚀刻工艺之后，可以去除掩模层。蚀刻气体可以包括磷（P）和氟（F）。 RF功率可以被恒定地或选择性地提供给处理室，或者可以选择性地提供不同级别的RF功率。当RF功率关闭或处于较低水平时，可将蚀刻气体供应到处理室。当RF功率开启或处于较高水平时，可以提供表面活化气体。

2. 发明授权

US09246082B2 Method of forming magnetic memory devices 有权
标题翻译：形成磁存储器件的方法
公开(公告)号：US09246082B2
公开(公告)日：2016-01-26
申请号：US14286407
申请日：2014-05-23
申请人： Ken Tokashiki
发明人： Ken Tokashiki
IPC分类号： H01L21/00 , H01L43/12 , H01L21/02 , H01L27/22
CPC分类号： H01L43/12 , G11C11/161 , H01L21/02071 , H01L27/222 , H01L27/224 , H01L27/226
摘要： Provided is a method of forming a magnetic memory device. A first magnetic layer, a tunnel barrier, and a second magnetic layer are deposited on a substrate. The second magnetic layer, the tunnel barrier, and the first magnetic layer are etched to form magnetic tunnel junction structures. An ion beam etching process is performed using an oxygen-containing source gas to remove etching by-products on sidewalls of the magnetic tunnel junction structure and to oxidize the sidewalls of the magnetic tunnel junction structures.
摘要翻译：提供一种形成磁存储器件的方法。在基板上沉积第一磁性层，隧道势垒和第二磁性层。蚀刻第二磁性层，隧道势垒和第一磁性层以形成磁性隧道结结构。使用含氧源气体进行离子束蚀刻工艺，以去除在磁性隧道结结构的侧壁上的蚀刻副产物并氧化磁性隧道结结构的侧壁。

3. 发明授权

US07988874B2 Method of fabricating semiconductor device and synchronous pulse plasma etching equipment for the same 有权
标题翻译：制造半导体器件和同步脉冲等离子体蚀刻设备的方法
公开(公告)号：US07988874B2
公开(公告)日：2011-08-02
申请号：US12913965
申请日：2010-10-28
申请人： Jeong-Yun Lee , Ken Tokashiki , Kyoung-Sub Shin , Jun-Ho Yoon , Hong Cho
发明人： Jeong-Yun Lee , Ken Tokashiki , Kyoung-Sub Shin , Jun-Ho Yoon , Hong Cho
IPC分类号： C03C15/00 , C03C25/68 , H01L21/302 , H01L21/461
CPC分类号： H01J37/32165 , H01J37/32082 , H01J37/32155
摘要： Provided are a method of fabricating a semiconductor device and synchronous pulse plasma etching equipment for the same. The method includes outputting a first radio frequency (RF) power and a control signal and outputting a second RF power. The first RF power is pulse-width modulated to have a first frequency and a first duty ratio, and is applied to a first electrode in a plasma etching chamber. The control signal includes information on a phase of the first RF power. The second RF power is pulse-width modulated to have the first frequency and a second duty ratio smaller than the first duty ratio, is applied to a corresponding second electrode among second electrodes in the plasma etching chamber, and is supplied for a time section in which the first RF power is supplied.
摘要翻译：提供一种半导体器件和同步脉冲等离子体蚀刻设备的制造方法。该方法包括输出第一射频（RF）功率和控制信号并输出第二RF功率。第一RF功率被脉冲宽度调制以具有第一频率和第一占空比，并且被施加到等离子体蚀刻室中的第一电极。控制信号包括关于第一RF功率的相位的信息。第二RF功率被脉冲宽度调制成具有小于第一占空比的第一频率和第二占空比，被施加到等离子体蚀刻室中的第二电极中的对应的第二电极，并且被提供给提供第一RF功率。

4. 发明申请

US20100130018A1 Synchronous pulse plasma etching equipment and method of fabricating a semiconductor device 有权
标题翻译：同步脉冲等离子体蚀刻设备及制造半导体器件的方法
公开(公告)号：US20100130018A1
公开(公告)日：2010-05-27
申请号：US12591602
申请日：2009-11-24
申请人： Ken Tokashiki , Hong Cho , Jeong-Dong Choe
发明人： Ken Tokashiki , Hong Cho , Jeong-Dong Choe
IPC分类号： H01L21/3065
CPC分类号： H01J37/32165 , H01J37/32082 , H01J37/32174
摘要： Synchronous pulse plasma etching equipment includes a first electrode and one or more second electrodes configured to generate plasma in a plasma etching chamber. A first radio frequency power output unit is configured to apply a first radio frequency power having a first frequency and a first duty ratio to the first electrode, and to output a control signal including information about a phase of the first radio frequency power. At least one second radio frequency power output unit is configured to apply a second radio frequency power having a second frequency and a second duty ratio to a corresponding second electrode among the second electrodes. The second radio frequency power output unit is configured to control the second radio frequency power to be synchronized with the first radio frequency power or to have a phase difference from the first radio frequency power in response to the control signal.
摘要翻译：同步脉冲等离子体蚀刻设备包括第一电极和被配置为在等离子体蚀刻室中产生等离子体的一个或多个第二电极。第一射频功率输出单元被配置为向第一电极施加具有第一频率和第一占空比的第一射频功率，并且输出包括关于第一射频功率的相位的信息的控制信号。至少一个第二射频功率输出单元被配置为将具有第二频率和第二占空比的第二射频功率应用于第二电极中的对应的第二电极。第二射频功率输出单元被配置为响应于控制信号控制与第一射频功率同步的第二射频功率或者与第一射频功率相位差。

5. 发明授权

US06372654B1 Apparatus for fabricating a semiconductor device and method of doing the same 有权
标题翻译：半导体装置的制造装置及其制作方法
公开(公告)号：US06372654B1
公开(公告)日：2002-04-16
申请号：US09543734
申请日：2000-04-05
申请人： Ken Tokashiki
发明人： Ken Tokashiki
IPC分类号： H01L213065
CPC分类号： H01L21/67069 , H01J37/321 , H01L21/32136
摘要： There is provided a method of fabricating a semiconductor device, including the steps of (a) generating plasma in the following conditions: (a1) an RF bias voltage has a frequency equal to or greater than 1 MHz, (a2) an RF source voltage has a frequency equal to or greater than 1 MHz, (a3) the RF source voltage is modulated by pulses in a cycle equal to or greater than 100 &mgr;sec, and (a4) pulse-on time is equal to or greater than 50 &mgr;sec, and (b) patterning multi-layered metal wirings by etching through the plasma The method makes it possible to reduce charging damage to a gate insulating film, even if wirings are further spaced away from adjacent ones and/or an antenna ratio of multi-layered metal wirings is further increased.
摘要翻译：提供了制造半导体器件的方法，包括以下步骤：（a）在以下条件下产生等离子体：（a1）RF偏置电压具有等于或大于1MHz的频率，（a2）RF源电压具有等于或大于1MHz的频率，（a3）RF源电压由等于或大于100个音频的周期的脉冲调制，并且（a4）脉冲开启时间等于或大于50个音频，和（b）通过等离子体蚀刻图案化多层金属配线。该方法可以减小对栅极绝缘膜的充电损伤，即使布线与相邻布线进一步间隔开，和/或多层天线的天线比金属布线进一步增加。

6. 发明授权

US09444033B2 Magnetic memory device and method of manufacturing the same 有权
标题翻译：磁记忆体装置及其制造方法
公开(公告)号：US09444033B2
公开(公告)日：2016-09-13
申请号：US14311238
申请日：2014-06-20
申请人： Yoonchul Cho , Ken Tokashiki
发明人： Yoonchul Cho , Ken Tokashiki
IPC分类号： H01L43/12 , H01L43/02 , H01L43/08 , H01L27/22
CPC分类号： H01L43/02 , G11C11/161 , H01L27/226 , H01L27/228 , H01L43/08 , H01L43/12
摘要： Magnetic memory devices and methods of manufacturing the same are disclosed. A method may include forming a magnetic tunnel junction layer on a substrate, forming mask patterns on the magnetic tunnel junction layer, and sequentially performing a plurality of ion implantation processes using the mask patterns as ion implantation masks to form an isolation region in the magnetic tunnel junction layer. The isolation region may thereby define magnetic tunnel junction parts that are disposed under corresponding ones of the mask patterns. A magnetic memory device may include a plurality of magnetic tunnel junction parts electrically and magnetically isolated from each other through the isolation region.
摘要翻译：公开了磁存储器件及其制造方法。一种方法可以包括在衬底上形成磁性隧道结层，在磁性隧道结层上形成掩模图案，并使用掩模图案依次执行多个离子注入工艺，作为离子注入掩模，以在磁隧道中形成隔离区结层。因此，隔离区域可以限定设置在相应的掩模图案下的磁性隧道结部分。磁存储器件可以包括通过隔离区域彼此电隔离和磁隔离的多个磁性隧道结部分。

7. 发明授权

US08592812B2 Device for analyzing charge and ultraviolet (UV) light 有权
标题翻译：用于分析电荷和紫外线（UV）光的装置
公开(公告)号：US08592812B2
公开(公告)日：2013-11-26
申请号：US12818569
申请日：2010-06-18
申请人： Ken Tokashiki
发明人： Ken Tokashiki
IPC分类号： H01L27/06
CPC分类号： H01L27/092 , H01L22/14 , H01L22/34
摘要： Provided is a device for analyzing at least one of a generated amount of positive charges, a generated amount of negative charges, and a generated amount of ultraviolet (UV) light. The device includes a substrate on which at least one of a first device configured to detect a variation in threshold voltage relative to the generated amount of positive charges, a second device configured to detect a variation in threshold voltage relative to the generated amount of negative charges, and a third device configured to detect a variation in threshold voltage relative to the generated amount of UV light is formed. Each of the first through third devices includes a first isolation region disposed in the substrate which define first and third active regions each of a first conductivity type and second and fourth active regions each of a second conductivity type different from the first conductivity type, first impurity regions disposed in the first active region and spaced apart from each other and having the second conductivity type, a floating gate crossing over the first active region between the first impurity regions and extending over the second active region, a second impurity region disposed in the second active region and having the first conductivity type, and a conductive structure electrically connected to the second impurity region.
摘要翻译：提供一种用于分析产生的正电荷量，产生的负电荷量和产生的紫外线（UV）光量中的至少一个的装置。该器件包括衬底，第一器件中的至少一个配置成相对于所产生的正电荷量检测阈值电压的变化，第二器件被配置为检测阈值电压相对于产生的负电荷量的变化并且形成用于检测阈值电压相对于所产生的UV光量的变化的第三装置。第一至第三装置中的每一个包括设置在基板中的第一隔离区域，其限定第一和第三有源区域，每个有源区域具有第一导电类型和第二和第四有源区域，每个有源区域具有不同于第一导电类型的第二导电类型，第一杂质设置在所述第一有源区中并且彼此间隔开并且具有所述第二导电类型的区域;跨越所述第一杂质区之间并在所述第二有源区上延伸的所述第一有源区上的浮栅，设置在所述第二有源区中的第二杂质区有源区并具有第一导电类型，导电结构与第二杂质区电连接。

8. 发明申请

US20130008867A1 METHODS FOR MANUFACTURING MAGNETIC TUNNEL JUNCTION STRUCTURE 审中-公开
标题翻译：制造磁性隧道结构的方法
公开(公告)号：US20130008867A1
公开(公告)日：2013-01-10
申请号：US13533385
申请日：2012-06-26
申请人： Ken Tokashiki , Hyung-Joon Kwon , Myeong-Cheol Kim
发明人： Ken Tokashiki , Hyung-Joon Kwon , Myeong-Cheol Kim
IPC分类号： H01F41/00
CPC分类号： H01F41/302 , B82Y40/00
摘要： Methods for manufacturing a magnetic tunnel junction structure include forming a magnetic tunnel junction (MTJ) layer by sequentially stacking a first ferromagnetic layer, a tunnel insulation layer, and a second ferromagnetic layer on a substrate, forming a mask pattern on the MTJ layer, and etching at least a portion of the MTJ layer in an etching chamber using the mask pattern as an etch mask, wherein the etching of the at least a portion of the MTJ layer includes applying a RF source power to a first electrode of the etching chamber as first RF power in a first pulselike mode, and applying a RF bias power to a second electrode of the etching chamber as second RF power in a second pulselike mode. The second pulselike mode of the RF bias power has a different phase from the first pulselike mode of the RF source power.
摘要翻译：用于制造磁性隧道结结构的方法包括通过在衬底上依次堆叠第一铁磁层，隧道绝缘层和第二铁磁层来形成磁隧道结（MTJ）层，在MTJ层上形成掩模图案，以及使用掩模图案蚀刻蚀刻室中的MTJ层的至少一部分作为蚀刻掩模，其中对MTJ层的至少一部分的蚀刻包括将RF源功率施加到蚀刻室的第一电极作为第一脉冲模式中的第一RF功率，以及以第二脉冲模式的第二RF功率将RF偏置功率施加到蚀刻室的第二电极。 RF偏置功率的第二脉动模式与RF源功率的第一脉动模式具有不同的相位。

9. 发明申请

US20120052689A1 PLASMA ETCHING METHOD AND APPARATUS THEREOF 审中-公开
标题翻译：等离子体蚀刻方法及其装置
公开(公告)号：US20120052689A1
公开(公告)日：2012-03-01
申请号：US12969660
申请日：2010-12-16
申请人： Ken Tokashiki
发明人： Ken Tokashiki
IPC分类号： H01L21/302 , C23F1/08
CPC分类号： H01L21/31116 , H01J37/32091 , H01J37/321 , H01J37/32155 , H01J2237/3347 , H01J2237/3348
摘要： A method of etching a substrate includes positioning the substrate on a substrate support within a chamber, etching a formation in the substrate in the presence of plasma within the chamber, decreasing a positive charge within the formation, and further etching the formation in the substrate in the presence of plasma after decreasing the positive charge within the formation.
摘要翻译：蚀刻衬底的方法包括将衬底定位在室内的衬底支撑件上，在室内存在等离子体的情况下蚀刻衬底中的地层，减少地层内的正电荷，以及进一步蚀刻衬底中的地层在降低地层内的正电荷之前，存在等离子体。

10. 发明授权

US06391772B1 Method for forming interconnects in semiconductor device 失效
标题翻译：在半导体器件中形成互连的方法
公开(公告)号：US06391772B1
公开(公告)日：2002-05-21
申请号：US09635104
申请日：2000-08-09
申请人： Ken Tokashiki , Eiichi Soda
发明人： Ken Tokashiki , Eiichi Soda
IPC分类号： H01L2144
CPC分类号： H01L21/76885 , H01L21/32136
摘要： A method for forming interconnects of a semiconductor device in which an amount of the fluorocarbon-based gas in an etching gas is adjusted to form a side-wall film which has a film thickness not less than a critical film thickness. In the present invention, the damage of a gate electrode and a gate dielectric film, due to charging imbalance caused by an electron shading effect during the etching of an interconnect layer, can be prevented.
摘要翻译：一种用于形成半导体器件的互连的方法，其中调整蚀刻气体中的氟碳基气体的量以形成膜厚不小于临界膜厚度的侧壁膜。在本发明中，可以防止由于在互连层的蚀刻期间由电子阴影效应引起的充电不平衡而导致的栅极电极和栅极电介质膜的损坏。

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