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1. 发明申请

US20080273291A1 Channel Method For Forming A Capacitor 有权
标题翻译：形成电容器的通道方法
公开(公告)号：US20080273291A1
公开(公告)日：2008-11-06
申请号：US12098593
申请日：2008-04-07
申请人： Keith R. Brenneman , Chris Wayne , Chris Stolarski , John T. Kinard , Alethia Melody , Gregory J. Dunn , Remy J. Chellni , Robert T. Croswell
发明人： Keith R. Brenneman , Chris Wayne , Chris Stolarski , John T. Kinard , Alethia Melody , Gregory J. Dunn , Remy J. Chellni , Robert T. Croswell
IPC分类号： H01G9/00
CPC分类号： H01G9/15 , H01G9/0029 , Y10T29/417
摘要： An improved method for forming a capacitor. The method includes: providing a carrier with a channel therein; providing a metal foil with a valve metal with a first dielectric on a first face of the metal foil; securing the metal foil into the channel with the first dielectric away from a channel floor; inserting an insulative material between the metal foil and each side wall of the channel; forming a cathode layer on the first dielectric between the insulative material; forming a conductive layer on the cathode layer and in electrical contact with the carrier; lap cutting the carrier parallel to the metal foil such that the valve metal is exposed; and dice cutting to form singulated capacitors.
摘要翻译：一种形成电容器的改进方法。该方法包括：在其中提供具有通道的载体; 在所述金属箔的第一面上提供具有第一电介质的阀金属的金属箔; 将金属箔固定到通道中，使第一电介质远离通道底板; 在金属箔和通道的每个侧壁之间插入绝缘材料; 在绝缘材料之间的第一电介质上形成阴极层; 在阴极层上形成导电层并与载体电接触; 搭载平行于金属箔的载体，使得阀金属暴露; 和骰子切割以形成单个电容器。

2. 发明授权

US07833292B2 Channel method for forming a capacitor 有权
标题翻译：用于形成电容器的通道方法
公开(公告)号：US07833292B2
公开(公告)日：2010-11-16
申请号：US12098593
申请日：2008-04-07
申请人： Keith R. Brenneman , Chris Wayne , Chris Stolarski , John T Kinard , Alethia Melody , Gregory J. Dunn , Remy J. Chelini , Robert T. Croswell
发明人： Keith R. Brenneman , Chris Wayne , Chris Stolarski , John T Kinard , Alethia Melody , Gregory J. Dunn , Remy J. Chelini , Robert T. Croswell
IPC分类号： H01G9/00
CPC分类号： H01G9/15 , H01G9/0029 , Y10T29/417
摘要： An improved method for forming a capacitor. The method includes providing a carrier with a channel therein, providing a metal foil with a valve metal with a first dielectric on a first face of the metal foil, securing the metal foil into the channel with the first dielectric away from a channel floor, inserting an insulative material between the metal foil and each side wall of the channel, forming a cathode layer on the first dielectric between the insulative material, forming a conductive layer on the cathode layer and in electrical contact with the carrier, lap cutting the carrier parallel to the metal foil such that the valve metal is exposed, and dice cutting to form singulated capacitors.
摘要翻译：一种形成电容器的改进方法。该方法包括在其中提供具有通道的载体，在金属箔的第一面上提供具有阀金属的金属箔，其具有第一电介质，将金属箔固定到通道中，使第一电介质远离通道底板，插入在金属箔和通道的每个侧壁之间的绝缘材料，在绝缘材料之间的第一电介质上形成阴极层，在阴极层上形成导电层并与载体电接触，将载体平行于金属箔使得金属金属暴露，并且切割切割以形成单个电容器。

3. 发明申请

US20100177460A1 CHANNEL METHOD FOR FORMING A CAPACITOR 审中-公开
标题翻译：用于形成电容器的通道方法
公开(公告)号：US20100177460A1
公开(公告)日：2010-07-15
申请号：US12726467
申请日：2010-03-18
申请人： Keith R. Brenneman , Chris Wayne , Chris Stolarski , John T. Kinard , Alethia Melody , Gregory J. Dunn , Remy J. Chelini , Robert T. Croswell
发明人： Keith R. Brenneman , Chris Wayne , Chris Stolarski , John T. Kinard , Alethia Melody , Gregory J. Dunn , Remy J. Chelini , Robert T. Croswell
IPC分类号： H01G4/008 , H01G4/00
CPC分类号： H01G9/15 , H01G9/0029
摘要： An improved method for forming a capacitor. The method includes: providing a carrier with a channel therein; providing a metal foil with a valve metal with a first dielectric on a first face of the metal foil; securing the metal foil into the channel with the first dielectric away from a channel floor; inserting an insulative material between the metal foil and each side wall of the channel; forming a cathode layer on the first dielectric between the insulative material; forming a conductive layer on the cathode layer and in electrical contact with the carrier; lap cutting the carrier parallel to the metal foil such that the valve metal is exposed; and dice cutting to form singulated capacitors.
摘要翻译：一种形成电容器的改进方法。该方法包括：在其中提供具有通道的载体; 在所述金属箔的第一面上提供具有第一电介质的阀金属的金属箔; 将金属箔固定到通道中，使第一电介质远离通道底板; 在金属箔和通道的每个侧壁之间插入绝缘材料; 在绝缘材料之间的第一电介质上形成阴极层; 在阴极层上形成导电层并与载体电接触; 搭载平行于金属箔的载体，使得阀金属暴露; 和骰子切割以形成单个电容器。

4. 发明申请

US20100020473A1 SUBSTRATE WITH EMBEDDED PATTERNED CAPACITANCE 有权
标题翻译：具有嵌入式图形电容的基板
公开(公告)号：US20100020473A1
公开(公告)日：2010-01-28
申请号：US12180768
申请日：2008-07-28
申请人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
发明人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
IPC分类号： H01G9/15
CPC分类号： H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
摘要： A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
摘要翻译：一种用于形成具有电容的叠层的方法和由此形成的层压体。该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。在电介质上形成导电层。处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

5. 发明授权

US08410536B2 Substrate with embedded patterned capacitance 有权
标题翻译：基板与嵌入式图案电容
公开(公告)号：US08410536B2
公开(公告)日：2013-04-02
申请号：US13345227
申请日：2012-01-06
申请人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
发明人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
IPC分类号： H01L27/108 , H01G4/005
CPC分类号： H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
摘要： A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
摘要翻译：一种用于形成具有电容的叠层的方法和由此形成的层压体。该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。在电介质上形成导电层。处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

6. 发明授权

US08470680B2 Substrate with embedded patterned capacitance 有权
公开(公告)号：US08470680B2
公开(公告)日：2013-06-25
申请号：US12180768
申请日：2008-07-28
申请人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
发明人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
IPC分类号： H01G4/005
CPC分类号： H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
摘要： A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

7. 发明申请

US20120106032A1 SUBSTRATE WITH EMBEDDED PATTERNED CAPACITANCE 有权
标题翻译：具有嵌入式图形电容的基板
公开(公告)号：US20120106032A1
公开(公告)日：2012-05-03
申请号：US13345227
申请日：2012-01-06
申请人： John D. Prymak , Chris Stolarski , Alethia Melody , Anthony P. Chacko , Gregory J. Dunn
发明人： John D. Prymak , Chris Stolarski , Alethia Melody , Anthony P. Chacko , Gregory J. Dunn
IPC分类号： H01G9/025 , H01G9/04 , H01G9/15 , H01G7/00
CPC分类号： H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
摘要： A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
摘要翻译：一种用于形成具有电容的叠层的方法和由此形成的层压体。该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。在电介质上形成导电层。处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

8. 发明申请

US20100315510A1 System and Method for Providing Depth Imaging 有权
标题翻译：提供深度成像的系统和方法
公开(公告)号：US20100315510A1
公开(公告)日：2010-12-16
申请号：US12483088
申请日：2009-06-11
申请人： Gregory J. Dunn , Robert T. Croswell , Zhiyuan Z. Li
发明人： Gregory J. Dunn , Robert T. Croswell , Zhiyuan Z. Li
IPC分类号： H04N7/18
CPC分类号： H04N5/272 , H04N5/2723
摘要： A device for use with an imaging system that is operable to provide an image signal based on an object disposed at a first distance from the imaging system. The imaging system includes a first camera, a second camera and a display. The first camera is operable to generate a first image signal based on the object and includes a first optics system and a first detector. The first optics system has a focal length, whereas the first detector has a resolution. The second camera is operable to generate a second image signal based on the object. The second camera includes a second optics system and a second detector. The second optics system has the same focal length of the first optics system and the second detector has the same resolution as the first detector. The second camera is separated from the first camera by a second distance. The display is operable to display an image based on a modified image. The device comprises an image processor that is operable to establish a virtual separation membrane and to output a modified image based on the first image signal, the second image signal, the virtual separation membrane, the second distance, the focal length and the resolution.
摘要翻译：一种与成像系统一起使用的装置，其可操作以基于设置在离成像系统第一距离处的物体提供图像信号。成像系统包括第一相机，第二相机和显示器。第一相机可操作以基于对象生成第一图像信号，并且包括第一光学系统和第一检测器。第一光学系统具有焦距，而第一检测器具有分辨率。第二相机可操作以基于对象生成第二图像信号。第二相机包括第二光学系统和第二检测器。第二光学系统具有与第一光学系统相同的焦距，第二检测器具有与第一检测器相同的分辨率。第二个相机与第一个相机分离第二个距离。显示器可操作以基于修改的图像显示图像。该装置包括图像处理器，其可操作以建立虚拟分离膜并且基于第一图像信号，第二图像信号，虚拟分离膜，第二距离，焦距和分辨率来输出修改的图像。

9. 发明授权

US07138068B2 Printed circuit patterned embedded capacitance layer 失效
公开(公告)号：US07138068B2
公开(公告)日：2006-11-21
申请号：US11084938
申请日：2005-03-21
申请人： Gregory J. Dunn , Robert T. Croswell , Jaroslaw A. Magera , Jovica Savic , Aroon V. Tungare
发明人： Gregory J. Dunn , Robert T. Croswell , Jaroslaw A. Magera , Jovica Savic , Aroon V. Tungare
IPC分类号： H01L21/302
CPC分类号： C23F1/40 , C23F1/02 , C23F1/32 , C23F1/34 , H05K1/162 , H05K3/0044 , H05K3/025 , H05K3/06 , H05K3/429 , H05K2201/0175 , H05K2201/0179 , H05K2201/09309 , H05K2201/09509 , H05K2203/025 , H05K2203/0746
摘要： A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

10. 发明授权

US07528788B2 High impedance electromagnetic surface and method 失效
标题翻译：高阻抗电磁表面和方法
公开(公告)号：US07528788B2
公开(公告)日：2009-05-05
申请号：US12174960
申请日：2008-07-17
申请人： Gregory J. Dunn , Robert T. Croswell , George H. Kumpf , John A. Svigelj
发明人： Gregory J. Dunn , Robert T. Croswell , George H. Kumpf , John A. Svigelj
IPC分类号： H01Q3/40
CPC分类号： H01Q15/006 , H05K1/116 , H05K1/162 , H05K1/165 , H05K3/429 , H05K3/4602 , H05K3/4688 , H05K2201/0187 , H05K2201/0715 , H05K2201/09509 , H05K2201/09609
摘要： A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).
摘要翻译：高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319）电路板（302）。多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器在印刷电路板（302）内。

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