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1. 发明申请

US20050243739A1 NETWORK TOPOLOGY DISCOVERY 审中-公开
标题翻译：网络拓扑发现
公开(公告)号：US20050243739A1
公开(公告)日：2005-11-03
申请号：US10907929
申请日：2005-04-21
申请人： Keith Anderson , Peter Weichhold , Christopher Simon
发明人： Keith Anderson , Peter Weichhold , Christopher Simon
IPC分类号： H04L12/24 , H04L12/26 , H04L29/12
CPC分类号： H04L29/12952 , H04L29/12009 , H04L29/12783 , H04L41/0213 , H04L41/12 , H04L61/35 , H04L61/6077
摘要： A method of assigning device identification in a switched network, and the resulting switched network, includes designing a network having a design topology made up of network devices, constructing a network from the designed network and discovering the actual topology of the constructed network. The discovered topology is compared with the design topology to assign identifications to network devices of the constructed network.
摘要翻译：一种在交换网络中分配设备识别的方法，以及所形成的交换网络，包括设计具有由网络设备构成的设计拓扑的网络，从所设计的网络构建网络并发现所构建的网络的实际拓扑。将发现的拓扑与设计拓扑进行比较，为构建的网络的网络设备分配标识。

2. 发明授权

US07788440B2 Method and device for coupling at least two independent bus systems 有权
标题翻译：用于耦合至少两个独立总线系统的方法和装置
公开(公告)号：US07788440B2
公开(公告)日：2010-08-31
申请号：US12085540
申请日：2006-11-27
申请人： Peter Weichhold
发明人： Peter Weichhold
IPC分类号： G06F13/38 , G06F13/36
CPC分类号： H04L12/4625 , G06F13/405 , H04L12/40058 , H04L12/40091
摘要： There is described a method for coupling at least two independent bus systems and to a suitable device for carrying out said method, a cycle time TA, TB being assigned to each bus system and each data item from a sequence of data being transmitted to the bus of the respective bus system in its own cycle. A predetermined or predeterminable number of data items is buffered from a data sequence that is to be transmitted from the original bus system to the target bus system, and a respective data item is determined on the basis of the cycle time TB of the target bus system from the data buffered on the basis of cycle time TA of the original bus system.
摘要翻译：描述了一种用于耦合至少两个独立总线系统和用于执行所述方法的合适设备的方法，将周期时间TA，TB分配给每个总线系统，并且每个数据项从被发送到总线的数据序列各自的公交系统在自己的周期。从要从原始总线系统发送到目标总线系统的数据序列缓冲预定或可预定数量的数据项，并且基于目标总线系统的周期时间TB来确定相应的数据项从基于原始总线系统的周期时间TA缓冲的数据。

3. 发明申请

US20090055561A1 Bus Module for Connection to a Bus System and Use of Such a Bus Module in an AS-I Bus System 有权
标题翻译：用于连接总线系统的总线模块和在AS-I总线系统中使用这种总线模块
公开(公告)号：US20090055561A1
公开(公告)日：2009-02-26
申请号：US12085269
申请日：2006-11-17
申请人： Gudrun Ritz , Peter Weichhold , Jurgen Wolski
发明人： Gudrun Ritz , Peter Weichhold , Jurgen Wolski
IPC分类号： G06F13/00
CPC分类号： G05B9/02
摘要： Disclosed is a bus module that can be connected to a bus system and comprises means for outputting safety-relevant signals in the form of repeated unambiguous code sequences. The bus module further comprises a first and second arithmetic unit with means for executing software programs. A code generator program of the first arithmetic unit generates a first partial code sequence of the code sequence while a code generator program of the second arithmetic unit generates the remaining portion of the code sequence as a second partial code sequence. Advantageously, a proper code sequence is output at the output of the bus module only when both arithmetic units function properly. A deviation in the code sequence that is output can then be detected by a monitor or actuator.
摘要翻译：公开了一种总线模块，其可以连接到总线系统，并且包括用于以重复的明确代码序列的形式输出安全相关信号的装置。总线模块还包括具有用于执行软件程序的装置的第一和第二运算单元。第一算术单元的代码生成程序生成代码序列的第一部分代码序列，而第二运算单元的代码生成程序生成代码序列的剩余部分作为第二部分代码序列。有利的是，只有当两个运算单元正常工作时，才能在总线模块的输出端输出适当的代码序列。然后可以由监视器或执行器检测输出的代码序列中的偏差。

4. 发明授权

US07844865B2 Bus module for connection to a bus system and use of such a bus module in an AS-i bus system 有权
标题翻译：用于连接总线系统的总线模块和在AS-i总线系统中使用这种总线模块
公开(公告)号：US07844865B2
公开(公告)日：2010-11-30
申请号：US12085269
申请日：2006-11-17
申请人： Gudrun Ritz , Peter Weichhold , Jürgen Wolski
发明人： Gudrun Ritz , Peter Weichhold , Jürgen Wolski
IPC分类号： G06F11/00
CPC分类号： G05B9/02
摘要： Disclosed is a bus module that can be connected to a bus system and comprises means for outputting safety-relevant signals in the form of repeated unambiguous code sequences. The bus module further comprises a first and second arithmetic unit with means for executing software programs. A code generator program of the first arithmetic unit generates a first partial code sequence of the code sequence while a code generator program of the second arithmetic unit generates the remaining portion of the code sequence as a second partial code sequence. Advantageously, a proper code sequence is output at the output of the bus module only when both arithmetic units function properly. A deviation in the code sequence that is output can then be detected by a monitor or actuator.
摘要翻译：公开了一种总线模块，其可以连接到总线系统，并且包括用于以重复的明确代码序列的形式输出安全相关信号的装置。总线模块还包括具有用于执行软件程序的装置的第一和第二运算单元。第一算术单元的代码生成程序生成代码序列的第一部分代码序列，而第二运算单元的代码生成程序生成代码序列的剩余部分作为第二部分代码序列。有利的是，只有当两个运算单元正常工作时，才能在总线模块的输出端输出适当的代码序列。然后可以由监视器或执行器检测输出的代码序列中的偏差。

5. 发明申请

US20090172239A1 Method and Device for Coupling at Least Two Independent Bus Systems 有权
标题翻译：最少两台独立总线系统耦合的方法和装置
公开(公告)号：US20090172239A1
公开(公告)日：2009-07-02
申请号：US12085540
申请日：2006-11-27
申请人： Peter Weichhold
发明人： Peter Weichhold
IPC分类号： G06F13/36
CPC分类号： H04L12/4625 , G06F13/405 , H04L12/40058 , H04L12/40091
摘要： There is described a method for coupling at least two independent bus systems and to a suitable device for carrying out said method, a cycle time TA, TB being assigned to each bus system and each data item from a sequence of data being transmitted to the bus of the respective bus system in its own cycle. A predetermined or predeterminable number of data items is buffered from a data sequence that is to be transmitted from the original bus system to the target bus system, and a respective data item is determined on the basis of the cycle time TB of the target bus system from the data buffered on the basis of cycle time TA of the original bus system.
摘要翻译：描述了一种用于耦合至少两个独立总线系统和用于执行所述方法的合适设备的方法，将周期时间TA，TB分配给每个总线系统，并且每个数据项从被发送到总线的数据序列各自的公交系统在自己的周期。从要从原始总线系统发送到目标总线系统的数据序列缓冲预定或可预定数量的数据项，并且基于目标总线系统的周期时间TB来确定相应的数据项从基于原始总线系统的周期时间TA缓冲的数据。

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