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1. 发明授权

US06401187B1 Memory access optimizing method 失效
标题翻译：内存访问优化方法
公开(公告)号：US06401187B1
公开(公告)日：2002-06-04
申请号：US09581361
申请日：2000-06-12
申请人： Keiko Motokawa , Hiroyasu Nishiyama , Sumio Kikuchi
发明人： Keiko Motokawa , Hiroyasu Nishiyama , Sumio Kikuchi
IPC分类号： G06F1208
CPC分类号： G06F8/4442 , G06F12/0862 , G06F2212/6028
摘要： The present invention provides a memory access optimizing method which judges an access method suitable for each of memory accesses and executes the preload optimization and prefetch optimization, according to the judgement result, for an architecture equipped with a prefetch mechanism to write the data on a main storage device into a cache memory and a preload mechanism to write the data on the main storage device into a register without writing it into the cache memory. The memory access method judging step analyzes whether or not there is a designation of a memory access method by a user. Moreover, the memory access method judging step investigates whether or not the data are already in a cache memory, whether or not the data compete with other data for a cache, whether or not the data are to be referred to again later, and whether or not the data fulfill the restriction on register resources.
摘要翻译：本发明提供了一种存储器访问优化方法，其判断适合于每个存储器访问的访问方法，并根据判断结果执行预加载优化和预取优化，对于具有预取机制的架构将数据写入主存储设备进入高速缓冲存储器和预载机制，以将主存储设备上的数据写入寄存器而不将其写入高速缓冲存储器。存储器访问方法判断步骤分析用户是否存在存储器访问方法的指定。此外，存储器访问方法判断步骤检查数据是否已经在高速缓冲存储器中，数据是否与高速缓存的其他数据进行竞争，无论以后是否再次参考数据，以及是否或者数据不符合注册资源的限制。

2. 发明申请

US20050144605A1 Information processing system and code generation method 审中-公开
标题翻译：信息处理系统和代码生成方法
公开(公告)号：US20050144605A1
公开(公告)日：2005-06-30
申请号：US10975437
申请日：2004-10-29
申请人： Keiko Motokawa , Shinichi Ito
发明人： Keiko Motokawa , Shinichi Ito
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： In an information processing system, a strip-mining process for a plurality of loops can be efficiently executed exactly intended by a user. A source program 206 includes strip-mining directives 401 and 402, which indicates a strip-mining applicable scope including two strip-mining target loops. A compiler converts the strip-mining applicable scope indicated by the strip-mining directives 401 and 402 into two inner loops and an outer loop surrounding the two inner loops, the inner loops being obtained by replacing each of the iterations of the two strip-mining target loops with a predetermined value and the outer loop having a number of steps corresponding to the predetermined value
摘要翻译：在信息处理系统中，可以由用户精确地执行多个循环的剥离过程。源程序206包括剥离指令401和402，其指示包括两个剥皮目标循环的剥离适用范围。编译器将剥离指令401和402指示的剥离适用范围转换成两个内部循环和围绕两个内部循环的外部循环，内部循环通过替换两个剥离采矿的每个迭代获得具有预定值的目标循环，并且外部循环具有对应于预定值的多个步骤

3. 发明授权

US07313787B2 Compiler and method for optimizing object codes for hierarchical memories 失效
标题翻译：用于优化分层存储器的目标代码的编译器和方法
公开(公告)号：US07313787B2
公开(公告)日：2007-12-25
申请号：US10665931
申请日：2003-09-19
申请人： Keiko Motokawa , Ichiro Kyushima , Shinichi Ito
发明人： Keiko Motokawa , Ichiro Kyushima , Shinichi Ito
IPC分类号： G06F9/45
CPC分类号： G06F8/4442 , G06F12/0862 , G06F2212/6028
摘要： Different optimizing methods are applied in response to such a memory hierarchy to which a program mainly accesses when the program is executed. A memory hierarchy to which a program mainly accesses is designated by a user with employment of either a compiler option designation or a designation statement contained in the program. In a compiler, a memory hierarchy designation is analyzed, and an optimizing process according to the designated memory hierarchy is carried out.
摘要翻译：响应于程序在执行程序时主要访问的这样的存储器层次，应用不同的优化方法。程序主要访问的存储器层次由用户指定，使用程序中包含的编译器选项指定或指定语句。在编译器中，分析存储器层次名称，并且执行根据指定的存储器层次结构的优化处理。

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