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1. 发明授权

US08096744B2 Wafer processing system, wafer processing method, and ion implantation system 有权
标题翻译：晶圆处理系统，晶圆加工方法和离子注入系统
公开(公告)号：US08096744B2
公开(公告)日：2012-01-17
申请号：US11254854
申请日：2005-10-21
申请人： Keiji Okada , Fumiaki Sato , Hiroaki Nakaoka
发明人： Keiji Okada , Fumiaki Sato , Hiroaki Nakaoka
IPC分类号： H01L21/677
CPC分类号： H01L21/67213 , H01L21/67201 , H01L21/67745
摘要： Two load lock chambers having a load lock pedestal are provided adjacent to a vacuum process chamber through a vacuum intermediate chamber. A passage opening is provided between the vacuum process chamber and the vacuum intermediate chamber. Two wafer retaining arms are installed between a platen device in the vacuum process chamber and the vacuum intermediate chamber. The two wafer retaining arms are reciprocatingly movable between the corresponding load lock pedestals and the platen device while passing through the passage opening and crossing with an overpass each other at different levels. By retaining an unprocessed wafer by one of the wafer retaining arms and retaining a processed wafer by the other wafer retaining arm, transfer of the unprocessed wafer from one of the load lock pedestals to the platen device and transfer of the processed wafer from the platen device to the other load lock pedestal are performed simultaneously.
摘要翻译：具有负载锁定基座的两个负载锁定室通过真空中间室邻近真空处理室设置。在真空处理室和真空中间室之间设有通道开口。两个晶片保持臂安装在真空处理室中的压板装置和真空中间室之间。两个晶片保持臂在相应的负载锁定基座和压板装置之间可往复运动，同时穿过通道开口并与不同级别的立交桥交叉。通过用晶片保持臂中的一个保持未加工的晶片并通过另一个晶片保持臂保持经处理的晶片，将未加工的晶片从负载锁定基座之一转移到压板装置，并将经处理的晶片从压板装置到另一个负载锁定基座同时进行。

2. 发明申请

US20060182532A1 Wafer processing system, wafer processing method, and ion implantation system 有权
标题翻译：晶圆处理系统，晶圆加工方法和离子注入系统
公开(公告)号：US20060182532A1
公开(公告)日：2006-08-17
申请号：US11254854
申请日：2005-10-21
申请人： Keiji Okada , Fumiaki Sato , Hiroaki Nakaoka
发明人： Keiji Okada , Fumiaki Sato , Hiroaki Nakaoka
IPC分类号： B65G1/00
CPC分类号： H01L21/67213 , H01L21/67201 , H01L21/67745
摘要： Two load lock chambers having a load lock pedestal are provided adjacent to a vacuum process chamber through a vacuum intermediate chamber. A passage opening is provided between the vacuum process chamber and the vacuum intermediate chamber. Two wafer retaining arms are installed between a platen device in the vacuum process chamber and the vacuum intermediate chamber. The two wafer retaining arms are reciprocatingly movable between the corresponding load lock pedestals and the platen device while passing through the passage opening and crossing with an overpass each other at different levels. By retaining an unprocessed wafer by one of the wafer retaining arms and retaining a processed wafer by the other wafer retaining arm, transfer of the unprocessed wafer from one of the load lock pedestals to the platen device and transfer of the processed wafer from the platen device to the other load lock pedestal are performed simultaneously.
摘要翻译：具有负载锁定基座的两个负载锁定室通过真空中间室邻近真空处理室设置。在真空处理室和真空中间室之间设有通道开口。两个晶片保持臂安装在真空处理室中的压板装置和真空中间室之间。两个晶片保持臂在相应的负载锁定基座和压板装置之间可往复运动，同时穿过通道开口并与不同级别的立交桥交叉。通过用晶片保持臂中的一个保持未加工的晶片并通过另一个晶片保持臂保持经处理的晶片，将未加工的晶片从负载锁定基座之一转移到压板装置，并将经处理的晶片从压板装置到另一个负载锁定基座同时进行。

3. 发明授权

US06800512B1 Method of forming insulating film and method of fabricating semiconductor device 失效
标题翻译：形成绝缘膜的方法和制造半导体器件的方法
公开(公告)号：US06800512B1
公开(公告)日：2004-10-05
申请号：US09662004
申请日：2000-09-14
申请人： Kazuichiro Itonaga , Akihiro Yamamoto , Hiroaki Nakaoka , Isao Miyanaga , Yoshinao Harada
发明人： Kazuichiro Itonaga , Akihiro Yamamoto , Hiroaki Nakaoka , Isao Miyanaga , Yoshinao Harada
IPC分类号： H01L2100
CPC分类号： H01L21/31654 , H01L21/02238 , H01L21/02252 , H01L21/28247 , H01L21/31662 , H01L21/32 , H01L21/32105 , H01L21/76224 , H01L21/823842 , H01L21/823857
摘要： With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.
摘要翻译：通过在室内保持包括氧的气氛，并且将晶片保持在低温下，在室内产生的等离子体朝向晶片偏置，并且晶片经受等离子体。暴露在晶片上的半导体层被氧化成氧化膜。因此，即使在室温下也可以形成与热氧化不同的氧化膜。该氧化适用于在清洁光致抗蚀剂膜时蚀刻的注入保护绝缘膜的恢复，多晶硅膜之间形成的台阶的松弛，沟槽内形成的台阶的松弛等。此外，在去除用于形成包括金属的栅电极的光致抗蚀剂膜之前，可以通过保持光致抗蚀剂膜的这种氧化来形成污染保护膜。

4. 发明授权

US5780898A Semiconductor device with a vertical field effect transistor and method of manufacturing the same 失效
标题翻译：具有垂直场效应晶体管的半导体器件及其制造方法
公开(公告)号：US5780898A
公开(公告)日：1998-07-14
申请号：US856697
申请日：1997-05-15
申请人： Tokuhiko Tamaki , Tatsuo Sugiyama , Hiroaki Nakaoka
发明人： Tokuhiko Tamaki , Tatsuo Sugiyama , Hiroaki Nakaoka
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/76 , H01L29/74 , H01L31/062
CPC分类号： H01L21/82385 , H01L21/823885 , H01L27/0922
摘要： On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon semiconductor layers, laterally paired second p-type silicon semiconductor layers, and laterally paired n-type silicon semiconductor layers, by an epitaxial growth method. On the second n-type silicon semiconductor layer on the right side, there are successively formed a third p-type silicon semiconductor layer, a third n-type silicon semiconductor layer and a fourth p-type silicon semiconductor layer. The left first n-type silicon semiconductor layer, left second p-type silicon semiconductor layer and left second n-type silicon semiconductor layer form a first insular multilayered portion forming an n-channel MOSFET. The third p-type silicon semiconductor layer, third n-type silicon semiconductor layer and fourth p-type silicon semiconductor layer form a second insular portion forming a p-channel MOSFET. A first gate electrode is formed on a side surface of the left second p-type silicon semiconductor layer with a gate insulating film therebetween, and a second gate electrode is formed on a side surface of the right third n-type silicon semiconductor layer with a gate insulating film therebetween.
摘要翻译：在由p型硅制成的半导体衬底上，以连续分层的方式形成第一p型硅半导体层，横向配对的第一n型硅半导体层，横向配对的第二p型硅半导体层，和横向配对的n型硅半导体层，通过外延生长法。在右侧的第二n型硅半导体层上，依次形成第三p型硅半导体层，第三n型硅半导体层和第四p型硅半导体层。左第一n型硅半导体层，左第二p型硅半导体层和左第二n型硅半导体层形成形成n沟道MOSFET的第一岛状多层部分。第三p型硅半导体层，第三n型硅半导体层和第四p型硅半导体层形成形成p沟道MOSFET的第二岛形部分。第一栅电极形成在左第二p型硅半导体层的侧表面上，栅极绝缘膜之间，第二栅电极形成在右第三n型硅半导体层的侧表面上，栅绝缘膜。

5. 发明授权

US5409847A Manufacturing method of CMOS transistor in which heat treatment at higher temperature is done prior to heat treatment at low temperature 失效
标题翻译：在低温下进行热处理之前，在较高温度下进行热处理的CMOS晶体管的制造方法
公开(公告)号：US5409847A
公开(公告)日：1995-04-25
申请号：US141727
申请日：1993-10-27
申请人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
发明人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/823814 , Y10S148/147
摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

6. 发明授权

US07033874B2 Method of forming insulating film and method of fabricating semiconductor device including plasma bias for forming a second insulating film 失效
标题翻译：形成绝缘膜的方法和制造包括用于形成第二绝缘膜的等离子体偏压的半导体器件的方法
公开(公告)号：US07033874B2
公开(公告)日：2006-04-25
申请号：US10863285
申请日：2004-06-09
申请人： Kazuichiro Itonaga , Akihiro Yamamoto , Hiroaki Nakaoka , Isao Miyanaga , Yoshinao Harada
发明人： Kazuichiro Itonaga , Akihiro Yamamoto , Hiroaki Nakaoka , Isao Miyanaga , Yoshinao Harada
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/302 , H01L21/461 , H01L21/31
CPC分类号： H01L21/31654 , H01L21/02238 , H01L21/02252 , H01L21/28247 , H01L21/31662 , H01L21/32 , H01L21/32105 , H01L21/76224 , H01L21/823842 , H01L21/823857
摘要： With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within a trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.
摘要翻译：通过在室内保持包括氧的气氛，并且将晶片保持在低温下，在室内产生的等离子体朝向晶片偏置，并且晶片经受等离子体。暴露在晶片上的半导体层被氧化成氧化膜。因此，即使在室温下也可以形成与热氧化不同的氧化膜。该氧化适用于在清洁光致抗蚀剂膜时蚀刻的注入保护绝缘膜的回收，多晶硅膜之间形成的台阶的松弛，沟槽内形成的台阶的松弛等。此外，在去除用于形成包括金属的栅电极的光致抗蚀剂膜之前，可以通过保持光致抗蚀剂膜的这种氧化来形成污染保护膜。

7. 发明授权

US06995415B2 Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06995415B2
公开(公告)日：2006-02-07
申请号：US10475115
申请日：2003-02-14
申请人： Hisashi Ogawa , Hiroaki Nakaoka , Atsuhiro Kajiya , Shin Hashimoto , Kyoko Egashira
发明人： Hisashi Ogawa , Hiroaki Nakaoka , Atsuhiro Kajiya , Shin Hashimoto , Kyoko Egashira
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/105 , H01L27/10894 , H01L27/10897
摘要： A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.
摘要翻译：存储单元晶体管和平面电容器设置在存储区域中，CMOS器件的两个晶体管都设置在逻辑电路区域中。平面电容器的电容电介质15和平板电极16b设置在与浅沟槽隔离层12a共同的沟槽上，并且沟槽的上部填充有电容电介质15和板电极16b。形成作为存储节点的n型扩散层19，其端部区域沿着沟槽的上部的一侧延伸到与浅沟槽隔离层12a重叠的区域。可以增加用作电容器的基板的一部分的面积，而不增加基板面积。

8. 发明申请

US20050003621A1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050003621A1
公开(公告)日：2005-01-06
申请号：US10853128
申请日：2004-05-26
申请人： Hiroaki Nakaoka , Kentaro Nakanishi , Hiroyuki Umimoto , Atsuhiro Kajiya
发明人： Hiroaki Nakaoka , Kentaro Nakanishi , Hiroyuki Umimoto , Atsuhiro Kajiya
IPC分类号： H01L27/092 , H01L21/265 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823842
摘要： As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.
摘要翻译：作为用于激活注入到栅电极中的杂质的第一热处理，进行长时间的低温热处理，其中几乎不会发生多晶硅中每个晶粒中的硼扩散，并且发生每个晶体边界中的硼扩散。接下来，作为第二热处理，进行其中发生在多晶硅层中的每个晶粒中的杂质扩散的短时间的高温处理，例如尖峰退火和闪光退火。

9. 发明授权

US06784080B2 Method of manufacturing semiconductor device by sputter doping 失效
标题翻译：通过溅射掺杂制造半导体器件的方法
公开(公告)号：US06784080B2
公开(公告)日：2004-08-31
申请号：US09840306
申请日：2001-04-24
申请人： Bunji Mizuno , Hiroaki Nakaoka , Michihiko Takase , Ichiro Nakayama
发明人： Bunji Mizuno , Hiroaki Nakaoka , Michihiko Takase , Ichiro Nakayama
IPC分类号： H01L2104
CPC分类号： H01L29/66106 , H01J37/32082 , H01J37/32192 , H01J37/32412 , H01J37/32678 , H01L21/2236
摘要： A semiconductor substrate and an impurity solid that comprises of impurity to be introduced to a diode formation region are held in a vacuum chamber. Inert or reactive gas is introduced into the vacuum chamber to generate plasma composed of the inert or reactive gas. A first voltage allowing the impurity solid to serve as a cathode for the plasma is applied to the said impurity solid and the said impurity solid is sputtered by ions in the plasma, thereby mixing the impurity within the said impurity solid into the plasma. A second voltage allowing a semiconductor substrate to serve as a cathode for the plasma is applied to the said semiconductor substrate, thereby directly introducing the impurity within the plasma to the surface portion of the diode formation region of the said semiconductor substrate, generating a impurity layer.
摘要翻译：将包含待引入到二极管形成区域的杂质的半导体衬底和杂质固体保持在真空室中。将惰性或反应性气体引入真空室以产生由惰性或反应性气体组成的等离子体。将杂质固体用作等离子体的阴极的第一电压施加到所述杂质固体上，并且所述杂质固体被等离子体中的离子溅射，从而将所述杂质固体内的杂质混合到等离子体中。将半导体衬底用作等离子体的阴极的第二电压被施加到所述半导体衬底，从而将等离子体内的杂质直接引入到所述半导体衬底的二极管形成区域的表面部分，产生杂质层。

10. 发明授权

US06337500B1 Semiconductor device and method for fabricating the same 失效
公开(公告)号：US06337500B1
公开(公告)日：2002-01-08
申请号：US09099195
申请日：1998-06-18
申请人： Hiroaki Nakaoka , Hiromasa Fujimoto , Atsushi Hori , Takashi Uehara , Takehiro Hirai
发明人： Hiroaki Nakaoka , Hiromasa Fujimoto , Atsushi Hori , Takashi Uehara , Takehiro Hirai
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78621 , Y10S438/91
摘要： In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions. Thus, it is possible to provide an SOI transistor causing no decrease in the source/drain breakdown voltage resulting from substrate floating effects and causing little OFF leakage current because of the activation of the parasitic transistor.

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