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1. 发明授权

US5214318A Semiconductor integrated circuit device having a signal transmission line pair interconnected by propagation delay time control resistance 失效
标题翻译：具有通过传播延迟时间控制电阻互连的信号传输线对的半导体集成电路设备
公开(公告)号：US5214318A
公开(公告)日：1993-05-25
申请号：US638568
申请日：1991-01-07
申请人： Keiichirou Nakanishi , Mararu Osanai , Minoru Yamada , Masakazu Yamamoto , Akira Masaki , Mitsuo Usami
发明人： Keiichirou Nakanishi , Mararu Osanai , Minoru Yamada , Masakazu Yamamoto , Akira Masaki , Mitsuo Usami
IPC分类号： H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/04 , H03F3/45 , H03K5/151 , H03K19/013 , H03K19/0175 , H03K19/018 , H04B3/00
CPC分类号： H03K5/151 , H03K19/0136 , H03K19/01831 , H01L2924/0002
摘要： A semiconductor integrated circuit device has, in one embodiment, a pair of signal transmission lines formed over and insulated from a semiconductor substrate, a first circuit formed in the semiconductor substrate and electrically connected with one end of the pair of signal transmission lines for sending an electric signal, and a second circuit formed in the semiconductor substrate and electrically connected with the other end of the pair of signal transmission lines for receiving the electric signal propagating over the transmission line pair. A control resistance is electrically connected between the pair of transmission lines at the above-mentioned other end for controlling a delay time of the signal propagating over the pair of signal transmission lines between the opposite ends of the pair of signal transmission lines.
摘要翻译：在一个实施例中，半导体集成电路器件具有形成在半导体衬底上并与其绝缘的一对信号传输线，形成在半导体衬底中并与该对信号传输线的一端电连接的第一电路，用于发送电信号和形成在半导体衬底中并与该对信号传输线的另一端电连接的第二电路，用于接收在传输线对上传播的电信号。控制电阻电连接在上述另一端的一对传输线之间，用于控制在一对信号传输线的相对端之间在一对信号传输线上传播的信号的延迟时间。

2. 发明授权

US4558395A Cooling module for integrated circuit chips 失效
标题翻译：集成电路芯片的冷却模块
公开(公告)号：US4558395A
公开(公告)日：1985-12-10
申请号：US604003
申请日：1984-04-26
申请人： Minoru Yamada , Akira Masaki , Masakazu Yamamoto , Keiichirou Nakanishi , Takashi Nishida , Takahiro Daikoku , Fumiyuki Kobayashi , Kuninori Imai
发明人： Minoru Yamada , Akira Masaki , Masakazu Yamamoto , Keiichirou Nakanishi , Takashi Nishida , Takahiro Daikoku , Fumiyuki Kobayashi , Kuninori Imai
IPC分类号： H01L23/36 , H01L23/433 , H01L23/473 , H05K7/20
CPC分类号： H01L23/4332 , H01L2224/16225
摘要： A cooling module for integrated circuit chips comprising a plurality of integrated circuit chips mounted on a wiring substrate, cooling members respectively provided for integrated circuit chips, each of the cooling members having therein space for circulating the coolant, and flexible pipes connected to respective cooling members, the coolant being caused to flow into or out of said space of said cooling member through the flexible pipes in order to remove heat from the integrated circuit chip.
摘要翻译：一种用于集成电路芯片的冷却模块，包括安装在布线基板上的多个集成电路芯片，分别设置用于集成电路芯片的冷却构件，每个冷却构件具有用于使冷却剂循环的空间，以及连接到各个冷却构件的柔性管道通过柔性管使冷却剂流入或流出所述冷却构件的所述空间，以便从集成电路芯片去除热量。

3. 发明授权

US5110664A Thick film and thin film composite substrate and electronic circuit apparatus using it 失效
标题翻译：厚膜和薄膜复合基板和电子电路设备
公开(公告)号：US5110664A
公开(公告)日：1992-05-05
申请号：US550553
申请日：1990-07-10
申请人： Keiichirou Nakanishi , Masakazu Yamamoto , Minoru Yamada
发明人： Keiichirou Nakanishi , Masakazu Yamamoto , Minoru Yamada
IPC分类号： H01L23/12 , H01L23/538 , H05K1/02 , H05K1/03 , H05K1/09 , H05K1/16 , H05K3/40 , H05K3/46
CPC分类号： H01L23/5384 , H01L23/5383 , H05K3/4605 , H01L2224/16225 , H01L2924/15192 , H01L2924/15312 , H01L2924/3011 , H05K1/0268 , H05K1/0306 , H05K1/092 , H05K1/167 , H05K2201/0154 , H05K2201/10318 , H05K2203/1581 , H05K3/4061 , Y10S428/901 , Y10T428/24322 , Y10T428/24802 , Y10T428/24917 , Y10T428/31721
摘要： A thick film and thin film composite wiring substrate for mounting integrated circuit chips thereon, comprising a thin film substrate including a signal wiring layer therein, a thick film substrate laminated together with the thin film substrate, and at least a part of signal wiring being formed as a signal wiring layer included in the thick film substrate.
摘要翻译：一种用于在其上安装集成电路芯片的厚膜和薄膜复合布线基板，包括其中包括信号布线层的薄膜基板，与薄膜基板一起层压的厚膜基板，以及形成信号布线的至少一部分作为包括在厚膜基板中的信号布线层。

4. 发明授权

US4954877A Chip carrier 失效
标题翻译：芯片载体
公开(公告)号：US4954877A
公开(公告)日：1990-09-04
申请号：US388071
申请日：1989-08-02
申请人： Keiichirou Nakanishi , Minoru Yamada , Masakazu Yamamoto , Satoru Ogihara , Hiroichi Shinohara , Hideo Suzuki
发明人： Keiichirou Nakanishi , Minoru Yamada , Masakazu Yamamoto , Satoru Ogihara , Hiroichi Shinohara , Hideo Suzuki
IPC分类号： H01L23/12 , H01L23/498 , H01L23/64 , H01L25/00
CPC分类号： H01L23/642 , H01L23/49827 , H01L2224/16 , H01L2224/16235 , H01L2224/73253 , H01L2924/01046 , H01L2924/09701 , H01L2924/15311 , H01L2924/16152
摘要： The present invention relates to a chip carrier, on which LSI chips are mounted and a chip carrier is disclosed, in which a region where power source throughholes are arranged and a region where signal throughholes are arranged are separated from each other and a coupling capacitor is formed only in the region where the power source throughholes are arranged with an intention to reduce noise.
摘要翻译：本发明涉及其上安装有LSI芯片的芯片载体和芯片载体，其中布置有电源通孔的区域和布置信号通孔的区域彼此分离，并且耦合电容器是仅在设置电源通孔的区域中形成，意图减少噪声。

5. 发明授权

US4626889A Stacked differentially driven transmission line on integrated circuit 失效
标题翻译：集成电路上堆叠的差分驱动传输线
公开(公告)号：US4626889A
公开(公告)日：1986-12-02
申请号：US682938
申请日：1984-12-18
申请人： Masakazu Yamamoto , Akira Masaki , Ryotaro Kamikawai
发明人： Masakazu Yamamoto , Akira Masaki , Ryotaro Kamikawai
IPC分类号： H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/64 , H01P3/08 , H01P3/18
CPC分类号： H01L23/64 , H01L23/522 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor integrated circuit structure including a semiconductor substrate having a large area adapted for a large scale integration, a circuit formed in the substrate for generating a pair of complementary signals, a pair of common potential level layers with an electrically insulating layer interposed therebetween, the common potential level layers being formed above and being electrically insulated from the substrate, and a pair of electric conductor pattern layers formed in the insulating layer for conducting the pair of complementary signals. The electric conductor pattern layers are arranged so as to be overlapped with each other in a direction substantially perpendicular to the large area substrate and so as to be substantially parallel with the large area substrate. The overall length of the electric conductor pattern layers is such that when an electric signal is conducted through an electric conductor in an IC having a length equal to the above-mentioned overall length, attenuation of the signal thereby is not negligible.
摘要翻译：一种半导体集成电路结构，包括具有适合于大规模集成的大面积的半导体衬底，形成在用于产生一对互补信号的衬底中的电路，一对具有介于其间的电绝缘层的公共电位电平层，公共电位层形成在上方并与衬底电绝缘，以及一对电导体图案层，形成在绝缘层中，用于引导该对互补信号。电导体图案层被布置成在与大面积基板大致垂直的方向上彼此重叠，并且与大面积基板大致平行。电导体图形层的总长度使得当电信号通过长度等于上述总长度的IC中的导电体传导时，信号的衰减不可忽略。

6. 发明授权

US07824058B2 Wake-up apparatus 有权
标题翻译：唤醒设备
公开(公告)号：US07824058B2
公开(公告)日：2010-11-02
申请号：US12094853
申请日：2006-11-24
申请人： Manabu Inoue , Masakazu Yamamoto
发明人： Manabu Inoue , Masakazu Yamamoto
IPC分类号： F21V33/00
CPC分类号： G04G15/003 , G04G11/00 , H05B37/0218 , H05B37/0281 , Y02B20/42 , Y02B20/46 , Y10S5/905
摘要： In a wake-up apparatus for waking up a sleeper by light stimulus, it wakes the sleeper comfortably without feeling glare. A lighting device has a first lighting unit at a position that a light emitting face cannot be observed directly by the sleeper, and a second lighting unit at a position that a light emitting face can be observed directly by the sleeper. A control device activates the lighting device a predetermined time before a preset wake-up time so as to vary illuminance of light emitted from the lighting device in an order of low illuminance, middle illuminance and high illuminance, to light only the first lighting unit in a low illuminance condition and a middle illuminance condition, and to light both of the first lighting unit and the second lighting unit in a high illuminance condition, and quickly varies from the middle illuminance condition to the high illuminance condition.
摘要翻译：在用光刺激唤醒睡眠者的唤醒装置中，它可以舒适地唤醒睡眠者，而不会眩光。照明装置具有在由睡眠者不能直接观察到发光面的位置处的第一照明单元，以及可以通过卧铺台直接观察发光面的位置处的第二照明单元。控制装置在预设的唤醒时间之前的预定时间激活照明装置，以便以低照度，中等照度和高照度的顺序改变从照明装置发射的光的照度，仅将第一照明装置低照度条件和中等照度条件，并且在高照度条件下点亮第一照明单元和第二照明单元，并且从中间照度条件到高照度条件快速变化。

7. 发明授权

US06330703B1 Method and circuit for determining the power consumption requirements for a semiconductor logic circuit and designing the circuit accordingly 失效
标题翻译：用于确定半导体逻辑电路的功耗要求并相应地设计电路的方法和电路
公开(公告)号：US06330703B1
公开(公告)日：2001-12-11
申请号：US09041121
申请日：1998-03-12
申请人： Tatsuya Saito , Masayoshi Yagyu , Hiroki Yamashita , Tsuneyo Chiba , Masakazu Yamamoto
发明人： Tatsuya Saito , Masayoshi Yagyu , Hiroki Yamashita , Tsuneyo Chiba , Masakazu Yamamoto
IPC分类号： G06F1750
CPC分类号： G01R31/3004 , G06F2217/78
摘要： A logic circuit determines the power consumption of a semiconductor integrated device by taking into consideration the variation of the rate of operation. A control signal (TEST) is applied to each control signal input port (Tin) of flip-flop circuits of flip-flop circuit groups and a logic gate circuit having a plurality of input ports A and B in a combined circuit group. If the control signal (TEST) is low, both the flip-flop circuits and the logic gate circuit operate normally. However, if the control signal (TEST) is high, each of them performs the power consumption test. Regardless of the value of input signals applied to input ports D1 and D2 of the flip-flop circuits, the flip-flop circuits are controlled to have a repetitive output signal of high and low levels at ports Q1 and Q2, in synchronism with a clock signal. Through this operation test, operational failure is reduced and the quality of semiconductor chip production is guaranteed, because it is possible to predict accurately the power consumption when designing the logic circuit due to the relationship between the rate of operation and the power consumption.
摘要翻译：逻辑电路通过考虑操作速率的变化来确定半导体集成器件的功耗。控制信号（TEST）被施加到组合电路组中具有多个输入端口A和B的触发器电路组的触发器电路的每个控制信号输入端口（Tin）和逻辑门电路。如果控制信号（TEST）低，触发器电路和逻辑门电路均正常工作。但是，如果控制信号（TEST）为高，则进行功耗测试。不管施加到触发器电路的输入端口D1和D2的输入信号的值如何，触发器电路被控制为具有在时钟Q1与Q2的端口Q1和Q2的高电平和低电平的重复输出信号信号。通过这种操作测试，可以降低运行故障，保证半导体芯片生产的质量，因为由于操作速率和功耗之间的关系，可以准确地预测设计逻辑电路时的功耗。

8. 发明授权

US06326443B1 Process for preparing ethylene polymer and catalyst used therefor 失效
标题翻译：用于制备乙烯聚合物和催化剂的方法
公开(公告)号：US06326443B1
公开(公告)日：2001-12-04
申请号：US09202284
申请日：1998-12-11
申请人： Takashi Monoi , Masakazu Yamamoto , Hidenobu Torigoe , Yoshimitsu Ishihara , Shintaro Inazawa
发明人： Takashi Monoi , Masakazu Yamamoto , Hidenobu Torigoe , Yoshimitsu Ishihara , Shintaro Inazawa
IPC分类号： C08F422
CPC分类号： C08F10/02 , C08F4/639 , C08F110/02 , C08F210/16 , C08F4/69 , C08F2500/12 , C08F210/14 , C08F4/025
摘要： A polymerization catalyst which exhibits a high activity and a good hydrogen response and thus is suitable for the production of an ethylene polymer having a wide molecular weight range can be obtained by a method using a chromium compound, an organic aluminum compound and a carrier and comprising the following steps (a) to (d): (a) contacting a chromium compound with a carrier in the presence or absence of a solvent; (b) adding an organic aluminum compound to said contacted substances at a temperature of not higher than 60° C. in an amount such that the mixing ratio of said organic aluminum compound to said chromium compound falls within the range of from 0.5/1 to 100/1 as calculated in terms of the ratio of aluminum atom/chromium atom (Al/Cr molar ratio) and that the following relationship (1) is satisfied: log10t≦0.33log10C+0.35 (1) wherein t represents the time (min) required until the organic aluminum compound is added to give an Al/Cr molar ratio of 10/1; and C represents the amount of the carrier used (Kg); (c) after the addition of the organic aluminum compound, stirring at a temperature of from 0° C. to 60° C. for 0.5 to 4 hours; and (d) removing the solvent used, unreacted matters and by-products at a temperature of not higher than 60° C. in such a manner that the following relationship (2) is satisfied: log10T≦0.23log10C+1.10 (2) wherein T represents the time required until the removal is completed; and C represents the amount of the carrier used (Kg).
摘要翻译：可以通过使用铬化合物，有机铝化合物和载体的方法获得表现出高活性和良好的氢响应并因此适用于生产具有宽分子量范围的乙烯聚合物的聚合催化剂，并且包含以下步骤（a）至（d）：（a）在存在或不存在溶剂的情况下使铬化合物与载体接触; （b）在不高于60℃的温度下向所述接触物质中加入有机铝化合物，其量使得所述有机铝化合物与所述铬化合物的混合比在0.5 / 1至 100/1，以铝原子/铬原子的比例（Al / Cr摩尔比）计算，满足以下关系式（1）：其中t表示添加有机铝化合物所需的时间（分钟）得到10/1的Al / Cr摩尔比; C代表使用的载体量（Kg）; （c）在加入有机铝化合物后，在0℃至60℃的温度下搅拌0.5至4小时; 和（d）以不高于60℃的温度除去所使用的溶剂，未反应物和副产物，使得满足以下关系式（2）：其中T表示除去之前所需的时间完成 C表示使用的载体的量（Kg）。

9. 发明授权

US5729550A Data transmitter-receiver 失效
标题翻译：数据发射机 - 接收机
公开(公告)号：US5729550A
公开(公告)日：1998-03-17
申请号：US618787
申请日：1996-03-20
申请人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
发明人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
IPC分类号： G06F5/06 , G06K5/04 , G11B5/00 , G11B20/20
CPC分类号： G06F5/06
摘要： In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.
摘要翻译：在信息处理系统中的多个单元之间发送和接收信号时，可以在由周期（频率）相同但不一定相位的异步时钟操作的电路之间发送和接收信号，从而允许信息处理系统在较短的时钟周期内运行。布置在通信路径中的延迟电路是可控的，使得与发送单元的时钟信号同步发送的数据与接收单元的时钟信号同步正确检索。此外，与发送单元的时钟信号同步地发送具有预定简单模式的数据，并且确定数据是否已被接收单元正确地接收。延迟电路由决定结果自动控制。

10. 发明授权

US5704768A Motor pump family of centrifugal pumps 失效
标题翻译：电机泵系列离心泵
公开(公告)号：US5704768A
公开(公告)日：1998-01-06
申请号：US713958
申请日：1996-09-12
申请人： Makoto Kobayashi , Masakazu Yamamoto , Yoshio Miyake
发明人： Makoto Kobayashi , Masakazu Yamamoto , Yoshio Miyake
IPC分类号： F04D13/14 , F04D15/00 , F04D29/42 , F04B3/00
CPC分类号： F04D13/14 , F04D15/0072 , F04D29/4266 , F05B2230/601
摘要： A motor pump group has a plurality of centrifugal pumps of the same nominal port diameter including a plurality of impellers having stepwise greater outside diameters for stepwise higher pump heads, and a plurality of respective motors for actuating the pumps. The pump heads are classified into a low head section and a high head section. The low head section is handled by a single-stage impeller, and the high head section is handled by multi-stage impellers. The centrifugal pumps have respective pressed-sheet pump casings. The outside diameters of the impellers are not required to be increased in the high head section, and the outside diameters of the pump casings fall in a relatively small range.
摘要翻译：电动泵组具有多个具有相同标称端口直径的离心泵，其包括具有阶梯式较大外径的多个叶轮，用于逐级更高的泵头，以及用于致动泵的多个相应的电动机。泵头分为低头部和高头部。低头部分由单级叶轮处理，高头部由多级叶轮处理。离心泵具有各自的压片泵壳体。在高头部分中不需要增加叶轮的外径，并且泵壳的外径落在相对较小的范围内。

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