专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06237120B1 Program patching of a ROM 失效
标题翻译：程序修补ROM
公开(公告)号：US06237120B1
公开(公告)日：2001-05-22
申请号：US08368758
申请日：1995-01-04
申请人： Keiichiro Shimada , Katsumi Matsuno , Sunao Furui
发明人： Keiichiro Shimada , Katsumi Matsuno , Sunao Furui
IPC分类号： G01R3128
CPC分类号： G06F9/268 , G06F8/66 , G06F9/328 , G06F11/08 , G06F11/1402
摘要： A micro-controller integrated on a single substrate and which includes a read-only information memory for storing firmware, an address controller for performing address control, and an input port for inputting information supplied thereto from a source external to the substrate further incorporates a correcting information storage memory for receiving correcting information input thereto from the source external to the substrate through the input port and storing the correcting information upon an initialization of the micro-controller, wherein the correcting information is indicative of a modification for a defective information part stored in the read-only information storage memory, and a switching circuit for selectively switching the access by the address controller from the defective information part in the read-only information storage memory to the correcting information in the correcting information storage memory.
摘要翻译：一种集成在单个基板上的微控制器，其包括用于存储固件的只读信息存储器，用于执行地址控制的地址控制器和用于输入从源于外部的源提供给其的信息的输入端口进一步包括校正信息存储存储器，用于通过所述输入端口从所述基板外部的源接收从其输入的校正信息，并且在所述微控制器的初始化时存储所述校正信息，其中所述校正信息指示存储在所述微控制器中的缺陷信息部分的修改只读信息存储存储器和用于选择性地将地址控制器的访问从只读信息存储存储器中的缺陷信息部分切换到校正信息存储存储器中的校正信息的切换电路。

2. 发明授权

US5623665A Electronic apparatus for patching a read-only memory 失效
标题翻译：用于修补只读存储器的电子设备
公开(公告)号：US5623665A
公开(公告)日：1997-04-22
申请号：US404115
申请日：1995-03-13
申请人： Keiichiro Shimada , Sunao Furui
发明人： Keiichiro Shimada , Sunao Furui
IPC分类号： G06F9/445 , G06F11/00
CPC分类号： G06F8/66
摘要： A unitary electronic device includes a CPU, a RAM, a ROM for storing a processing program for the CPU which program includes a command to execute, at each processing cycle of the CPU, the processing located at a predetermined address in the RAM, and an input means or the like, for entering in the RAM at the predetermined address, information for correcting a defect in the processing program stored in the ROM.
摘要翻译：单片电子设备包括CPU，RAM，用于存储CPU处理程序的ROM，该程序包括在CPU的每个处理周期执行位于RAM中的预定地址的处理的命令，以及输入装置等，用于在预定地址处输入RAM，用于校正存储在ROM中的处理程序中的缺陷的信息。

3. 发明授权

US06580462B2 Television broadcast receiving system 有权
标题翻译：电视广播接收系统
公开(公告)号：US06580462B2
公开(公告)日：2003-06-17
申请号：US09252888
申请日：1999-02-18
申请人： Hajime Inoue , Shinji Kakuyama , Sunao Furui , Susumu Nagano
发明人： Hajime Inoue , Shinji Kakuyama , Sunao Furui , Susumu Nagano
IPC分类号： H04N1100
CPC分类号： H04N21/4184 , H04N5/4401 , H04N5/76 , H04N5/907 , H04N9/8042 , H04N21/434 , H04N21/4424 , H04N21/8153 , H04N21/8173
摘要： A television receiver apparatus has large versatility to adapt itself to newly offered services or new modes of use. An external memory element loaded with a flash memory is connected to the receiver apparatus through an external memory interface having a connector and an interface circuit. The external memory element stores information such as a program for implementing an additional function or data such as video and audio data. The information stored in the external memory element is taken up by the receiver apparatus through the external memory interface. The information from the external memory element is processed by a controlling portion of the receiver apparatus so as to be subjected to use.
摘要翻译：电视接收机设备具有很大的通用性，以适应新提供的服务或新的使用模式。装载有闪速存储器的外部存储器元件通过具有连接器和接口电路的外部存储器接口连接到接收器装置。外部存储器元件存储诸如用于实现附加功能的程序或诸如视频和音频数据的数据的信息。存储在外部存储元件中的信息由接收机装置通过外部存储器接口占据。来自外部存储元件的信息由接收机装置的控制部分处理，以便被使用。

4. 发明授权

US5619678A Electronic device for correction of ROM data with a parameter for calculation of position of correction data 失效
标题翻译：用于校正ROM数据的电子设备，具有用于计算校正数据位置的参数
公开(公告)号：US5619678A
公开(公告)日：1997-04-08
申请号：US122904
申请日：1993-09-16
申请人： Iwao Yamamoto , Sunao Furui
发明人： Iwao Yamamoto , Sunao Furui
IPC分类号： G06F9/06 , G06F9/42 , G06F9/445 , G06F11/28 , G06F15/78 , G06F12/06
CPC分类号： G06F9/4426 , G06F8/66
摘要： An electronic device having an integrated structure including central processing means for performing an access control to storage means, a calculation processing, etc., fixed storage means, input means for inputting correction information for correcting information of a specific part stored in the fixed storage means, correction information storage means for storing the correction information input from the input means, and change-over means for switching the access by the central processing means from an area in which a specific part of the information in the fixed storage means is stored, from the fixed storage means to the correction information storage means. The correction information includes at least batch correction data for correcting the information of the specific part and a parameter for calculating a storage position of the batch correction data in the correction information storage means.
摘要翻译：具有集成结构的电子设备，包括用于对存储装置执行访问控制的中央处理装置，计算处理等，固定存储装置，用于输入用于校正存储在固定存储装置中的特定部分的信息的校正信息的输入装置用于存储从输入装置输入的校正信息的校正信息存储装置，以及用于通过中央处理装置从存储固定存储装置中的信息的特定部分的区域切换存取的切换装置，固定存储装置到校正信息存储装置。校正信息至少包括用于校正特定部分的信息的批次校正数据和用于计算校正信息存储装置中批量校正数据的存储位置的参数。

5. 发明授权

US07034851B1 Receiver and method of controlling graphic display 有权
标题翻译：接收器和控制图形显示的方法
公开(公告)号：US07034851B1
公开(公告)日：2006-04-25
申请号：US09601940
申请日：1999-12-15
申请人： Sunao Furui , Toshisada Ishii , Naoki Murayama , Tatsuya Wakahara , Hidetaka Inada
发明人： Sunao Furui , Toshisada Ishii , Naoki Murayama , Tatsuya Wakahara , Hidetaka Inada
IPC分类号： G09G5/00
CPC分类号： H04N5/445 , G09G5/14 , G09G2340/125 , H04N5/44504 , H04N21/42653 , H04N21/431 , H04N21/4532 , H04N21/454 , H04N21/482 , H04N21/4882
摘要： The present invention is a multi-function receiver that controls a plurality of graphic user interface displays. The receiver includes a first display processing section for performing graphic display processing based on a program stored in a memory, a second display processing section for performing graphic display processing based on a control signal included in a signal for a channel being received, and a control section connected to the memory for controlling the first and second display processing sections. The control section performs control so to display a graphic screen display-processed by one of the first and second display processing sections. Thereby, the graphic screen display-processed by the first display processing section and the graphic screen display-processed by the second display processing section can be prevented from being overlapped and moreover, the conventional control program used in the first display processing section can be utilized as it is, without being changed.
摘要翻译：本发明是控制多个图形用户界面显示的多功能接收器。接收机包括：第一显示处理部分，用于基于存储在存储器中的程序执行图形显示处理;第二显示处理部分，用于基于包括在接收的信道的信号中的控制信号执行图形显示处理;以及控制连接到存储器的部分，用于控制第一和第二显示处理部分。控制部进行控制，以显示由第一和第二显示处理部中的一个显示处理的图形画面。由此，可以防止由第一显示处理部显示处理的图形画面和由第二显示处理部显示处理的图形画面重叠，此外，可以利用在第一显示处理部中使用的常规控制程序因为它是，没有改变。

6. 发明授权

US07023991B1 Method and apparatus for digital signal processing 有权
标题翻译：数字信号处理方法和装置
公开(公告)号：US07023991B1
公开(公告)日：2006-04-04
申请号：US09889374
申请日：2000-11-17
申请人： Masashi Nakamura , Hisayoshi Moriwaki , Sunao Furui , Ichiro Hamada
发明人： Masashi Nakamura , Hisayoshi Moriwaki , Sunao Furui , Ichiro Hamada
IPC分类号： H04K1/06 , H04K1/04
CPC分类号： H04N21/418 , H04N5/4401 , H04N5/46 , H04N7/163 , H04N7/1675 , H04N21/42607 , H04N21/4408 , H04N21/44231 , H04N21/8166 , H04N2005/4441
摘要： Elements necessary for a digital television receiver are structured as a plurality of digital signal processing blocks and a host arithmetic operation processing block. The blocks are connected through a general purpose bus. Commands for controlling operations of the blocks and data of a stream are transferred through the bus. When an encryption encoder/decode is disposed in each block, contents transferred through the bus can be protected. When an encryption encoder/decode circuit is disposed in an interface to which an extension plug-in card is attached, contents that are output from the interface can be protected.
摘要翻译：数字电视接收机所需的元件被构造为多个数字信号处理块和主算术运算处理块。这些块通过通用总线连接。用于控制流的块和数据的操作的命令通过总线传送。当在每个块中设置加密编码器/解码器时，可以保护通过总线传送的内容。当加密编码器/解码电路被布置在附接有扩展插件卡的接口中时，可以保护从接口输出的内容。

7. 发明授权

US07844991B1 Method and apparatus for digital signal processing 失效
标题翻译：数字信号处理方法和装置
公开(公告)号：US07844991B1
公开(公告)日：2010-11-30
申请号：US09889380
申请日：2000-11-17
申请人： Masashi Nakamura , Hisayoshi Moriwaki , Sunao Furui , Ichiro Hamada
发明人： Masashi Nakamura , Hisayoshi Moriwaki , Sunao Furui , Ichiro Hamada
IPC分类号： H04N7/20
CPC分类号： H04N21/426 , H04N5/4401 , H04N7/163 , H04N21/4316 , H04N21/4424 , H04N21/47 , H04N21/818
摘要： Elements necessary for a digital television receiver are structured as a plurality of digital signal processing blocks and a host operation processing block. The blocks are connected through a general-purpose bus. Command for controlling the operations of the blocks and data of streams are transferred through the bus. Thus, by replacing only blocks, various types of digital television broadcasts that differ in carrier waves, modulating systems, and compressing systems can be handled. Consequently, the developing efficiency of a television receiver is improved. In addition, when a new service is started, by adding hardware for the service, the service can be easily handled.
摘要翻译：数字电视接收机所需的元件被构造为多个数字信号处理块和主机操作处理块。这些块通过通用总线连接。通过总线传送用于控制数据块和数据流的操作的命令。因此，通过仅替换块，可以处理在载波，调制系统和压缩系统上不同的各种类型的数字电视广播。因此，提高了电视接收机的显影效率。另外，当新服务启动时，通过为服务添加硬件，可以轻松处理该服务。

8. 发明授权

US07096461B1 Method and apparatus for digital signal processing and method of providing extension function 失效
标题翻译：用于数字信号处理的方法和装置以及提供扩展功能的方法
公开(公告)号：US07096461B1
公开(公告)日：2006-08-22
申请号：US09889459
申请日：2000-11-17
申请人： Masashi Nakamura , Hisayoshi Moriwaki , Sunao Furui , Ichiro Hamada
发明人： Masashi Nakamura , Hisayoshi Moriwaki , Sunao Furui , Ichiro Hamada
IPC分类号： G06F9/45 , G06F9/44 , G06F15/00
CPC分类号： H04N21/4183 , G06F9/4411 , G06F15/7867 , H04N5/4401 , H04N21/426 , H04N21/8166
摘要： Elements necessary for a digital television receiver are structured as blocks that are a plurality of digital signal processing blocks and a host arithmetic operation processing block. The blocks are connected through a general-purpose bus. Commands for controlling operations of the blocks and data of streams are transferred through the bus. An extension plug-in card for a new service can be attached and detached to/from the bus. The extension plug-in card has hardware that accomplishes an extension function and a script for commands of the hardware. When the extension plug-in card is attached to the bus through an interface, the script for the commands is automatically uploaded to the host arithmetic operation processing block side. The host arithmetic operation processing block can operate the extension plug-in card corresponding to the transferred script for the commands.
摘要翻译：数字电视接收机所需的元件被构造为多个数字信号处理块和主算术运算处理块的块。这些块通过通用总线连接。用于控制流的块和数据的操作的命令通过总线传送。用于新服务的扩展插件卡可以连接到/从总线分离。扩展插件卡具有实现扩展功能的硬件和用于硬件命令的脚本。当扩展插件卡通过接口连接到总线时，命令的脚本将自动上传到主机算术运算处理模块侧。主机算术运算处理块可以对与命令的传送脚本相对应的扩展插件卡进行操作。

9. 发明授权

US06380984B1 Digital television broadcast receiving apparatus 有权
标题翻译：数字电视广播接收装置
公开(公告)号：US06380984B1
公开(公告)日：2002-04-30
申请号：US09255522
申请日：1999-02-22
申请人： Hajime Inoue , Sunao Furui
发明人： Hajime Inoue , Sunao Furui
IPC分类号： H04N550
CPC分类号： H04N21/42653 , H04N5/44508 , H04N21/235 , H04N21/4147 , H04N21/4184 , H04N21/434 , H04N21/435 , H04N21/4622 , H04N21/4782 , H04N21/482
摘要： A decoder has a DRAM used as a work area in processing such as decompression and an MPEG decoder including an OSD processing unit. The MPEG decoder has a function to decompress data completing MPEG compression and a graphic function to display information such as an EPG (Electronic Program Guide). A control unit generates display data from presentation information conveyed by a digital television broadcast by using the OSD processing unit employed in the MPEG decoder and the DRAM in order to display the presentation information. With such a decoder, it is possible to provide a receiver with a new function to use presentation information conveyed by a digital television broadcast without entailing an increase in cost.
摘要翻译：解码器具有用作诸如解压缩的处理中的工作区的DRAM和包括OSD处理单元的MPEG解码器。 MPEG解码器具有解压缩完成MPEG压缩的数据和图形功能以显示诸如EPG（Electronic Program Guide）的信息的功能。控制单元通过使用MPEG解码器和DRAM中采用的OSD处理单元从数字电视广播传送的演示信息生成显示数据，以便显示呈现信息。通过这样的解码器，可以向接收机提供使用数字电视广播传达的演示信息的新功能，而不增加成本。

10. 发明授权

US5731972A Electronic apparatus which inhibits control of certain objects during initialization processing 失效
标题翻译：在初始化处理期间禁止某些物体的控制的电子设备
公开(公告)号：US5731972A
公开(公告)日：1998-03-24
申请号：US650212
申请日：1996-05-20
申请人： Iwao Yamamoto , Sunao Furui
发明人： Iwao Yamamoto , Sunao Furui
IPC分类号： G06F9/06 , G06F11/00 , G06F11/14 , G06F11/28 , G11B5/02 , G11B15/02 , H04N5/238 , H04N5/765 , H04N5/782 , G06F19/00
CPC分类号： G06F11/1417
摘要： An electronic apparatus incorporating a microcomputer capable of correcting bugs by means of patches. The microcomputer circumvents serious trouble which would usually be produced due to bugs when the power supply is turned on. After the power supply is turned on and initialization of the microcomputer itself is complete, it is determined whether the initialization processing for correcting by patches has ended. If this processing has not yet ended, the microcomputer is inhibited from controlling certain objects (e.g., circuits for driving motors that control the tape transport mechanism of a video camera) which would cause serious trouble if they were to malfunction. The microcomputer control of other objects is not so inhibited. After the end of the initialization for correcting by patches, a program capable of correcting by patches is executed.
摘要翻译：一种包含微型计算机的电子设备，能够通过补丁来纠正错误。微型计算机规避了电源打开时由于错误而通常产生的严重问题。在电源接通并且微计算机本身的初始化完成之后，确定用于通过补丁校正的初始化处理是否已经结束。如果该处理尚未结束，则禁止微型计算机控制某些物体（例如，用于驱动控制摄像机的磁带传送机构的电动机的电路），如果它们发生故障将导致严重的故障。其他物体的微电脑控制不受此限制。在通过补丁校正的初始化结束之后，执行能够通过补丁校正的程序。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式