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1. 发明授权

US07369618B2 Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US07369618B2
公开(公告)日：2008-05-06
申请号：US11132206
申请日：2005-05-19
申请人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
发明人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
IPC分类号： H04B3/00
CPC分类号： H04L25/028 , H04L25/0292 , H04L25/03878
摘要： A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.
摘要翻译：与重复分别表示准备期间和发送期间的H，L电平的时钟信号同步地发送信号。发送电路包括发送电容器，用于在准备期间根据发送电容器中的输入数字信号设定电压的输入开关和用于在发送期间产生信号线中的小电压变化的发送开关，根据发送电容器的电压进行变化。接收电路包括具有CMOS配置的反相器，插入在反相器的输入端子和输出端子之间的接收电容器，用于使逆变器的输入端子和输出端子短路的均衡开关，以便设置电压的信号线在预备期间达到预定电压，以及锁存器，用于通过在每个传输周期内执行对逆变器的输出端子的电压的逻辑放大来提供输出数字信号，并且用于保持每个准备周期的输出。

2. 发明申请

US20050207504A1 Signal transmission circuit 失效
公开(公告)号：US20050207504A1
公开(公告)日：2005-09-22
申请号：US11132206
申请日：2005-05-19
申请人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
发明人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
IPC分类号： H03K19/096 , H03K17/04 , H03K19/0175 , H04L25/02 , H04L25/03 , H04L25/00
CPC分类号： H04L25/028 , H04L25/0292 , H04L25/03878
摘要： A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.

3. 发明授权

US06922443B1 Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US06922443B1
公开(公告)日：2005-07-26
申请号：US09712247
申请日：2000-11-15
申请人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
发明人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
IPC分类号： H03K19/096 , H03K17/04 , H03K19/0175 , H04L25/02 , H04L25/03 , H04B3/00
CPC分类号： H04L25/028 , H04L25/0292 , H04L25/03878
摘要： A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.
摘要翻译：与重复分别表示准备期间和发送期间的H，L电平的时钟信号同步地发送信号。发送电路包括发送电容器，用于在准备期间根据发送电容器中的输入数字信号设定电压的输入开关和用于在发送期间产生信号线中的小电压变化的发送开关，根据发送电容器的电压进行变化。接收电路包括具有CMOS配置的反相器，插入在反相器的输入端子和输出端子之间的接收电容器，用于使逆变器的输入端子和输出端子短路的均衡开关，以便设置电压的信号线在预备期间达到预定电压，以及锁存器，用于通过在每个传输周期内执行对逆变器的输出端子的电压的逻辑放大来提供输出数字信号，并且用于保持每个准备周期的输出。

4. 发明授权

US5671181A Data read circuit used in semiconductor storage device 失效
标题翻译：数据读取电路用于半导体存储设备
公开(公告)号：US5671181A
公开(公告)日：1997-09-23
申请号：US573146
申请日：1995-12-15
申请人： Tsuguyasu Hatsuda
发明人： Tsuguyasu Hatsuda
IPC分类号： G11C7/06 , G11C8/08 , G11C8/10 , G11C7/00
CPC分类号： G11C7/062 , G11C7/067 , G11C8/08 , G11C8/10
摘要： When a data is read out from a memory cell, a current mirror circuit is operated in response to detection of potential variation of a first data line, so that charge of a second data line is discharged by the current mirror circuit. At this point, a control transistor interposed between the first data line and the second data line is operated in a saturation region. As a result, the impedance between the first data line and the second data line becomes substantially infinity, and the two data lines are substantially open-circuited. Thus, the current mirror circuit discharges merely the second data line with a small load capacitance in a short period of time, resulting in a high speed read operation. Therefore, even when the first data line, to which a large number of memory cells are connected, has a large load capacitance, the read rate is increased.
摘要翻译：当从存储器单元读出数据时，响应于检测到第一数据线的电位变化而操作电流镜电路，使得第二数据线的电荷被电流镜电路放电。此时，夹在第一数据线和第二数据线之间的控制晶体管在饱和区域中工作。结果，第一数据线和第二数据线之间的阻抗变得基本上无限大，并且两条数据线基本上是开路的。因此，电流镜像电路仅在短时间内仅放电具有小负载电容的第二数据线，导致高速读取操作。因此，即使当连接有大量存储单元的第一数据线具有大的负载电容时，读取速率也增加。

5. 发明授权

US5391938A Comparator using XNOR and XOR gates 失效
标题翻译：比较器使用XNOR和XOR门
公开(公告)号：US5391938A
公开(公告)日：1995-02-21
申请号：US157602
申请日：1993-11-24
申请人： Tsuguyasu Hatsuda
发明人： Tsuguyasu Hatsuda
IPC分类号： G06F12/08 , G11C8/00 , H03K5/22 , H03K19/21
CPC分类号： G11C8/00 , G06F12/0895
摘要： A comparator for comparing the voltages of an address pair signals in complement with the voltages of bit pair signals in complement includes a pair of transistors for receiving the bit pair signals and a pair of MOSFETs for receiving the address pair signals. One transistor and one MOSFET are connected in series to define a first current path and other transistor and other MOSFET are connected in series to define a second current path. When the address signal and the bit signal are the same, both the first and second current paths close, but when they are different, either the first or the second current path opens to permit a current to pass therethrough. By detecting the current in the path, the coincidence and non-coincidence between the address pair signals and bit pair signals are detected.
摘要翻译：用于将补码中的地址对信号的电压与补码中的位对信号的电压进行比较的比较器包括用于接收位对信号的一对晶体管和用于接收地址对信号的一对MOSFET。一个晶体管和一个MOSFET串联连接以限定第一电流路径，并且其它晶体管和其它MOSFET串联连接以限定第二电流路径。当地址信号和位信号相同时，第一和第二电流路径都闭合，但是当它们不同时，第一或第二电流路径打开以允许电流通过。通过检测路径中的电流，检测地址对信号和位对信号之间的一致性和不一致性。

6. 发明授权

US5289414A Comparator 失效
标题翻译：比较器
公开(公告)号：US5289414A
公开(公告)日：1994-02-22
申请号：US951166
申请日：1992-09-25
申请人： Tsuguyasu Hatsuda
发明人： Tsuguyasu Hatsuda
IPC分类号： G06F12/08 , G11C8/00 , G11C7/00
CPC分类号： G11C8/00 , G06F12/0895
摘要： A comparator for comparing the voltage of an address pair signals in complement with the voltages of bit pair signals in complement includes a pair of transistors for receiving the bit pair signals and a pair of MOSFETs for receiving the address pair signals. One transistor and one MOSFET are connected in series to define a first current path and other transistor and other MOSFET are connected in series to define a second current path. When the address signal and the bit signal are the same, both the first and second current paths close, but when they are different; either the first or the second current path opens to permit a current to pass therethrough. By detecting the current in the path, the coincidence and non-coincidence between the address pair signals and bit pair signals are detected.
摘要翻译：用于将补码中的地址对信号的电压与补码中的位对信号的电压进行比较的比较器包括用于接收位对信号的一对晶体管和用于接收地址对信号的一对MOSFET。一个晶体管和一个MOSFET串联连接以限定第一电流路径，并且其它晶体管和其它MOSFET串联连接以限定第二电流路径。当地址信号和位信号相同时，第一和第二电流路径都接近，但是当它们不同时; 第一或第二电流通路打开以允许电流通过。通过检测路径中的电流，检测地址对信号和位对信号之间的一致性和不一致性。

7. 发明授权

US5576565A MIS capacitor and a semiconductor device utilizing said MIS capacitor 失效
标题翻译： MIS电容器和利用所述MIS电容器的半导体器件
公开(公告)号：US5576565A
公开(公告)日：1996-11-19
申请号：US220282
申请日：1994-03-30
申请人： Seiji Yamaguchi , Tsuguyasu Hatsuda , Ichirou Matsuo
发明人： Seiji Yamaguchi , Tsuguyasu Hatsuda , Ichirou Matsuo
IPC分类号： H01L27/08 , H01L29/94 , H01L27/108 , H01L21/70 , H01L29/76
CPC分类号： H01L29/94 , H01L27/0805
摘要： The present invention discloses the structure of a MIS capacitor adapted to be interposed between two terminals, i.e., first and second terminals, to be connected to an electric circuit. Formed on a common semiconductor substrate are first and second capacity insulator layers, first and second electrically conductive layers thereon, and first and second impurity diffusion areas under the first and second capacity insulator layers. Also formed are a first wiring line which connects the first electrically conductive layer and the second impurity diffusion area to the first terminal, and a second wiring line which connects the second electrically conductive layer and the first impurity diffusion area to the second terminal. Accordingly, the first electrically conductive layer and the second impurity diffusion area form one electrode, while the second electrically conductive layer and the first impurity diffusion area form the other electrode. With the arrangement above-mentioned, voltage dependencies inherent in capacitors each having a MIS structure are substantially cancelled with each other, resulting in reduction of the voltage dependency of the MIS capacitor. Through a process using one polysilicon layer, there can be formed an economical MIS capacitor having a small area which can be mounted on an analog circuit.
摘要翻译：本发明公开了一种适于插入到两个端子即第一和第二端子之间以连接到电路的MIS电容器的结构。形成在公共半导体衬底上的第一和第二电容绝缘体层，其上的第一和第二导电层以及第一和第二电容绝缘体层下的第一和第二杂质扩散区。还形成有将第一导电层和第二杂质扩散区域连接到第一端子的第一布线和将第二导电层和第一杂质扩散区域连接到第二端子的第二布线。因此，第一导电层和第二杂质扩散区域形成一个电极，而第二导电层和第一杂质扩散区域形成另一个电极。利用上面的布置，各自具有MIS结构的电容器中固有的电压依赖性基本上彼此抵消，导致MIS电容器的电压依赖性降低。通过使用一个多晶硅层的工艺，可以形成经济的MIS电容器，其具有可以安装在模拟电路上的小面积。

8. 发明授权

US5559456A Sensing circuit unit for a dynamic circuit 失效
标题翻译：用于动态电路的感应电路单元
公开(公告)号：US5559456A
公开(公告)日：1996-09-24
申请号：US106551
申请日：1993-08-16
申请人： Tsuguyasu Hatsuda
发明人： Tsuguyasu Hatsuda
IPC分类号： G11C7/06 , H03K5/02 , H03F3/45
CPC分类号： G11C7/067 , H03K5/026
摘要： In the present invention, there are disposed (i) a P-channel MOSFET for detecting variations of the voltage level of a data line to supply an electric current, and (ii) a current mirror circuit to which an electric current from the P-channel MOSFET is entered as a reference current and of which output current terminal is connected to the data line. When the data line is lowered in voltage level so that an electric current flows from the P-channel MOSFET to the current mirror circuit, an output current of the current mirror circuit flows to the drain of an N-channel MOSFET, so that the data line is electrically discharged. Thus, there is achieved a sensing circuit unit which is suitably used for a dynamic circuit and which can detect, at a high speed, variations of the voltage level of the data line as precharged.
摘要翻译：在本发明中，设置（i）用于检测数据线的电压电平的变化以提供电流的P沟道MOSFET，以及（ii）电流镜电路，其中来自P- 通道MOSFET作为参考电流输入，其输出电流端子连接到数据线。当数据线在电压电平下降使得电流从P沟道MOSFET流到电流镜电路时，电流镜电路的输出电流流向N沟道MOSFET的漏极，使得数据线线路电气放电。因此，实现了适合用于动态电路的感测电路单元，并且可以高速检测预充电的数据线的电压电平的变化。

9. 发明申请

US20050258887A1 Level shifter having automatic delay adjusting function 有权
标题翻译：电平移位器具有自动延时调整功能
公开(公告)号：US20050258887A1
公开(公告)日：2005-11-24
申请号：US11191009
申请日：2005-07-28
申请人： Miwa Ito , Kazuyuki Nakanishi , Akio Hirata , Hiroo Yamamoto , Tsuguyasu Hatsuda
发明人： Miwa Ito , Kazuyuki Nakanishi , Akio Hirata , Hiroo Yamamoto , Tsuguyasu Hatsuda
IPC分类号： H03K19/0185 , H03K3/011 , H03K3/356 , H03K5/153 , H03L5/00
CPC分类号： H03K3/356113 , H03K3/011
摘要： In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit. Accordingly, even when at least one of the amplitude voltage of the input signal and the amplitude voltage of the output signal is changed, balance between the fall delay time characteristic and the rise delay time characteristic of the output signal can be satisfactorily kept.
摘要翻译：在电平移位器中，输入到输入端子的输入信号（即，第一电源电压VDDL）的振幅电压变化为较高，输出信号的振幅电压（即，第二电源电压从输出端子输出的VDDH）变低，从输出端子输出的信号的下降延迟时间趋于长于信号的上升延迟时间。然而，由逆变器获得的反相输入信号被输入到电平移位单元，并输入到N型晶体管的栅极，因此，在输入信号的输入信号的下降时，N型晶体管导通输入端子，以便将基于第二电源电压VDDH的电流提供给电平移位单元的输出节点，用于辅助在电平转换单元中执行的向H电平的移位。因此，即使当输入信号的振幅电压和输出信号的振幅电压中的至少一个改变时，也能够令人满意地保持输出信号的下降延迟时间特性和上升延迟时间特性之间的平衡。

10. 发明授权

US6066177A Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library 失效
公开(公告)号：US6066177A
公开(公告)日：2000-05-23
申请号：US917210
申请日：1997-08-25
申请人： Tsuguyasu Hatsuda
发明人： Tsuguyasu Hatsuda
IPC分类号： H01L29/00 , G06F17/50 , H01L21/82
CPC分类号： G06F17/5022
摘要： In a delay-power-source-coefficient determining step, a drain saturation current in a P-channel MOSFET is calculated on the basis of specified operating power-source voltage data and of saturation-current parameters such as the mobility of carriers and the thickness of a gate oxide film based on said specified operating power-source voltage data. Thereafter, a ratio of a drain saturation current in the P-channel MOSFET when a reference power-source voltage is applied thereto to the drain saturation current in the P-channel MOSFET when an operating power-source voltage is applied thereto, thereby determining a delay power-source coefficient. Next, in an effective-delay calculating step, effective-delay calculating means multiplies a delay time when the reference power-source voltage calculated by the delay calculating means is applied thereto by the delay power-source coefficient calculated by delay-power-source-coefficient determining means to determine a delay time at the operating power-source voltage.

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