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1. 发明授权

US08273633B2 Method of enhancing dopant activation without suffering additional dopant diffusion 有权
标题翻译：增加掺杂剂激活而不会受到额外的掺杂剂扩散的方法
公开(公告)号：US08273633B2
公开(公告)日：2012-09-25
申请号：US11690869
申请日：2007-03-26
申请人： Keh-Chiang Kuo , Chien-Hao Chen , Chun-Feng Nieh , Li-Ping Huang , Hsun Chang , Li-Ting Wang , Chih-Chiang Wang , Tze-Liang Lee
发明人： Keh-Chiang Kuo , Chien-Hao Chen , Chun-Feng Nieh , Li-Ping Huang , Hsun Chang , Li-Ting Wang , Chih-Chiang Wang , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/2658 , H01L21/2686 , H01L21/324 , H01L21/823814 , H01L21/823878
摘要： A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.
摘要翻译：增加掺杂剂激活而不会受到额外的掺杂剂扩散的方法包括在半导体衬底中形成浅掺杂的和轻掺杂的源极/漏极扩展区，在源极/漏极延伸区上执行第一退火工艺，形成深和重掺杂的源/ 漏极区域，并且在源极/漏极区域上执行第二退火处理。第一退火工艺是在约1毫秒至3毫秒之间的时间内执行的闪光退火工艺，第二退火工艺是在约1秒至30秒之间进行的快速热退火工艺。

2. 发明授权

US07741699B2 Semiconductor device having ultra-shallow and highly activated source/drain extensions 有权
标题翻译：半导体器件具有超浅的和高激活的源极/漏极延伸
公开(公告)号：US07741699B2
公开(公告)日：2010-06-22
申请号：US11521660
申请日：2006-09-15
申请人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
发明人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/00
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/0847 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.
摘要翻译：半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

3. 发明申请

US20080242039A1 METHOD OF ENHANCING DOPANT ACTIVATION WITHOUT SUFFERING ADDITIONAL DOPANT DIFFUSION 有权
标题翻译：不增加添加剂掺合物增加钆激活的方法
公开(公告)号：US20080242039A1
公开(公告)日：2008-10-02
申请号：US11690869
申请日：2007-03-26
申请人： Keh-Chiang Ku , Chien-Hao Chen , Chun-Feng Nieh , Li-Ping Huang , Hsun Chang , Li-Ting Wang , Chih-Chiang Wang , Tze-Liang Lee
发明人： Keh-Chiang Ku , Chien-Hao Chen , Chun-Feng Nieh , Li-Ping Huang , Hsun Chang , Li-Ting Wang , Chih-Chiang Wang , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/2658 , H01L21/2686 , H01L21/324 , H01L21/823814 , H01L21/823878
摘要： A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.
摘要翻译：增加掺杂剂激活而不会受到额外的掺杂剂扩散的方法包括在半导体衬底中形成浅掺杂的和轻掺杂的源极/漏极扩展区，在源极/漏极延伸区上执行第一退火工艺，形成深和重掺杂的源/ 漏极区域，并且在源极/漏极区域上执行第二退火处理。第一退火工艺是在约1毫秒至3毫秒之间的时间内执行的闪光退火工艺，第二退火工艺是在约1秒至30秒之间进行的快速热退火工艺。

4. 发明申请

US20070284615A1 Ultra-shallow and highly activated source/drain extension formation using phosphorus 有权
标题翻译：使用磷的超浅和高活化的源/漏延伸形成
公开(公告)号：US20070284615A1
公开(公告)日：2007-12-13
申请号：US11521660
申请日：2006-09-15
申请人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
发明人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/739
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/0847 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.
摘要翻译：半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

5. 发明授权

US08058134B2 Junction profile engineering using staged thermal annealing 有权
标题翻译：接头型材工程采用分段热退火
公开(公告)号：US08058134B2
公开(公告)日：2011-11-15
申请号：US12618052
申请日：2009-11-13
申请人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
发明人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
摘要翻译：退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。第二个持续时间比第一个持续时间长。退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。

6. 发明申请

US20100210086A1 Junction Profile Engineering Using Staged Thermal Annealing 有权
标题翻译：接头型材工程使用分段热退火
公开(公告)号：US20100210086A1
公开(公告)日：2010-08-19
申请号：US12618052
申请日：2009-11-13
申请人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
发明人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
摘要翻译：退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。第二个持续时间比第一个持续时间长。退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。

7. 发明授权

US08828817B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08828817B2
公开(公告)日：2014-09-09
申请号：US13356207
申请日：2012-01-23
申请人： Wei-Yuan Lu , Li-Ping Huang , Han-Ting Tsai , Wei-Ching Wang , Ming-Shuan Li , Hsueh-Jen Yang , Kuan-Chung Chen
发明人： Wei-Yuan Lu , Li-Ping Huang , Han-Ting Tsai , Wei-Ching Wang , Ming-Shuan Li , Hsueh-Jen Yang , Kuan-Chung Chen
IPC分类号： H01L21/8238
CPC分类号： H01L29/7849 , B82Y10/00 , H01L21/26506 , H01L21/324 , H01L29/32 , H01L29/6653 , H01L29/6656 , H01L29/7613 , H01L29/7843 , H01L29/7848
摘要： A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.
摘要翻译：形成半导体器件的方法包括在衬底上执行第一预非晶体注入工艺，其中衬底具有栅叠层。该方法还包括在衬底上形成第一应力膜。该方法还包括对基板和第一应力膜执行第一退火处理。该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。

8. 发明授权

US08348686B1 Plug security structure for electrical connector 有权
标题翻译：电连接器插头安全结构
公开(公告)号：US08348686B1
公开(公告)日：2013-01-08
申请号：US13270745
申请日：2011-10-11
申请人： Li-Ping Huang
发明人： Li-Ping Huang
IPC分类号： H01R13/44
CPC分类号： H01R13/6272 , H01R13/6392
摘要： A plug security structure includes a plug, a cable, a jacket, a movable cap and a key. By means of a middle block, the movable cap is slidably insertable into sliding grooves in between two upright sidewalls of a front bracket of the jacket to stop the front stop block and to have outer ribs of the elastic retaining members of the movable cap be stopped at rear end edges of the sliding grooves in the upright sidewalls of the front bracket, preventing the latch from downward displacement to unlock the plug from the mating jack and assuring a high level of network data transmission safeness. The cap has a raised portion for friction engagement with the bottom surface of the stop wall of the front bracket of the jacket, preventing vibration or displacement of the movable cap and assuring positive operation of the latch of the plug.
摘要翻译：插头安全结构包括插头，电缆，护套，可动盖和钥匙。通过中间块，可移动盖可滑动地插入到护套的前支架的两个直立侧壁之间的滑动槽中，以阻止前止动块并且使可动盖的弹性保持构件的外肋停止在前支架的直立侧壁中的滑动槽的后端边缘处，防止闩锁向下移位，以使插头从配合插座解锁，并确保高水平的网络数据传输安全性。盖具有用于与护套的前支架的止动壁的底表面摩擦接合的凸起部分，防止可动盖的振动或位移，并确保插头的闩锁的正向操作。

9. 发明授权

US07732877B2 Gated diode with non-planar source region 有权
标题翻译：具有非平面源极区域的栅极二极管
公开(公告)号：US07732877B2
公开(公告)日：2010-06-08
申请号：US11731963
申请日：2007-04-02
申请人： Da-Wen Lin , Ying-Shiou Lin , Shyh-Wei Wang , Li-Ping Huang , Ying-Keung Leung , Carlos H. Diaz
发明人： Da-Wen Lin , Ying-Shiou Lin , Shyh-Wei Wang , Li-Ping Huang , Ying-Keung Leung , Carlos H. Diaz
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7391 , H01L29/0657 , H01L29/42312 , H01L29/66356
摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.
摘要翻译：门控二极管半导体器件或类似部件及其制造方法。该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且邻近源极和漏极。源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。如果两者都存在，则源极和漏极可以是对称的或非对称的。这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

10. 发明申请

US20080237746A1 Gated diode with non-planar source region 有权
标题翻译：具有非平面源极区域的栅极二极管
公开(公告)号：US20080237746A1
公开(公告)日：2008-10-02
申请号：US11731963
申请日：2007-04-02
申请人： Da-Wen Lin , Ying-Shiou Lin , Shyh-Wei Wang , Li-Ping Huang , Ying-Keung Leung , Carlos H. Diaz
发明人： Da-Wen Lin , Ying-Shiou Lin , Shyh-Wei Wang , Li-Ping Huang , Ying-Keung Leung , Carlos H. Diaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/0657 , H01L29/42312 , H01L29/66356
摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.
摘要翻译：门控二极管半导体器件或类似部件及其制造方法。该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且与源极和漏极相邻。源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。如果两者都存在，则源极和漏极可以是对称的或非对称的。这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

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