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1. 发明授权

US06918074B2 At speed testing asynchronous signals 失效
标题翻译：在速度测试异步信号
公开(公告)号：US06918074B2
公开(公告)日：2005-07-12
申请号：US10187474
申请日：2002-06-28
申请人： Kee Sup Kim , Shyang-Tai Sean Su , Adarsh Kalliat , Ajith Prasad
发明人： Kee Sup Kim , Shyang-Tai Sean Su , Adarsh Kalliat , Ajith Prasad
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3187 , G01R31/3193 , G06F11/00 , G06F11/267
CPC分类号： G06F11/267
摘要： A testing device uses an input signature register to conduct “at speed” testing of asynchronous circuit responses in an effort to determine the operability of a monitored circuit. Upon receiving an enable signal, the input signature register quickly measures, compresses, and transmits the tested circuit responses so that the responses can be compared with a set of anticipated responses to determine whether the circuit is functioning properly. The enabled input signature register, such as a MISR or a SISR, generates an output signature, which contains the compressed responses of the monitored circuit and helps the testing device analyze circuit performance.
摘要翻译：测试设备使用输入签名寄存器对异步电路响应进行“速度”测试，以确定被监视电路的可操作性。一旦接收到使能信号，输入签名寄存器将快速测量，压缩和发送所测试的电路响应，使得可以将响应与一组预期响应进行比较，以确定电路是否正常工作。启用的输入签名寄存器（如MISR或SISR）生成输出签名，其包含受监控电路的压缩响应，并帮助测试设备分析电路性能。

2. 发明授权

US07523371B2 System and shadow bistable circuits coupled to output joining circuit 失效
标题翻译：耦合到输出接合电路的系统和阴影双稳态电路
公开(公告)号：US07523371B2
公开(公告)日：2009-04-21
申请号：US11218979
申请日：2005-09-02
申请人： Subhasish Mitra , Ming Zhang , Kee Sup Kim
发明人： Subhasish Mitra , Ming Zhang , Kee Sup Kim
IPC分类号： G01R31/28 , G06F7/02 , G06F13/00
CPC分类号： G01R31/318536 , G01R31/318525
摘要： In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.
摘要翻译：在一个实施例中，设备提供组合逻辑电路以产生数据输入信号; 耦合到组合逻辑电路的延迟元件，以响应于数据输入信号提供延迟的数据输入信号。另外，该装置设置有耦合到组合逻辑电路的系统双稳态电路，以响应于至少数据输入信号产生系统双稳态信号; 耦合到延迟元件的阴影双稳态电路，以响应于至少延迟的数据输入信号产生阴影双稳态信号。此外，该装置设置有耦合到系统和阴影双稳态电路的输出接合电路，以响应于系统和阴影双稳态信号提供数据输出信号。

3. 发明授权

US07574640B2 Compacting circuit responses 有权
标题翻译：压缩电路响应
公开(公告)号：US07574640B2
公开(公告)日：2009-08-11
申请号：US10656013
申请日：2003-09-05
申请人： Subhasish Mitra , Kee Sup Kim
发明人： Subhasish Mitra , Kee Sup Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves determining the number of unknown logic values that may be encountered and adding columns to the compactor matrix based on the number of errors. Basically, the number of possible combinations of scan in lines is determined. Then, additional columns are added for each possible combination of scan in lines. The number of columns that are added for each combination of scan in lines is equal to the number of errors plus one in one embodiment.
摘要翻译：压实机具有减少的输出数量和处理更多数量的错误和未知逻辑值的能力。设计矩阵和产生的压实机的过程涉及确定可能遇到的未知逻辑值的数量，并且基于错误数量向压实器矩阵添加列。基本上，确定线中扫描的可能组合的数量。然后，为行中扫描的每种可能组合添加其他列。为行中的扫描的每个组合添加的列数等于错误数量加上一个实施例中的列数。

4. 发明授权

US07240260B2 Stimulus generation 有权
标题翻译：刺激生成
公开(公告)号：US07240260B2
公开(公告)日：2007-07-03
申请号：US10317605
申请日：2002-12-11
申请人： Subhasish Mitra , Kee Sup Kim
发明人： Subhasish Mitra , Kee Sup Kim
IPC分类号： G01R31/3183 , G01R31/316
CPC分类号： G01R31/318547
摘要： In one embodiment, a method is provided. In the method of this embodiment, a stimulus signal set may be generated and supplied, as input, to first circuitry. Each respective stimulus signal in the stimulus signal set may be generated based at least in part upon a respective non-null subset of an input signal set. No two respective stimulus signals in the stimulus signal set may be generated based upon the same respective non-null subset of the input signal set. The stimulus signal set may include a respective number of stimulus signals that is greater than a respective number of input signals in the input signal set. Of course, many modifications, variations, and alternatives are possible without departing from the method of this embodiment.
摘要翻译：在一个实施例中，提供了一种方法。在本实施例的方法中，可以产生刺激信号组并作为输入提供给第一电路。可以至少部分地基于输入信号组的相应非零子集来生成刺激信号组中的各个刺激信号。基于输入信号组的相同的非零子集，可以在刺激信号组中不产生两个相应的刺激信号。刺激信号组可以包括大于输入信号组中相应数量的输入信号的相应数量的激励信号。当然，在不脱离本实施例的方法的情况下，可以进行许多修改，变化和替代。

5. 发明授权

US07814383B2 Compacting circuit responses 失效
标题翻译：压缩电路响应
公开(公告)号：US07814383B2
公开(公告)日：2010-10-12
申请号：US11251664
申请日：2005-10-17
申请人： Subhasish Mitra , Kee Sup Kim
发明人： Subhasish Mitra , Kee Sup Kim
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318566 , G01R31/3172 , G01R31/318547
摘要： Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.
摘要翻译：对于刺激的电路响应可能被压缩，使用压实器减少引脚数，而不增加电路元件的长度。根据本发明的一个实施例，可以在用于集成电路测试的扫描链中检测到错误。施加到输出引脚或其他连接器的输出的数量可以显着减少，从而节省成本。

6. 发明授权

US07278074B2 System and shadow circuits with output joining circuit 有权
标题翻译：具有输出接合电路的系统和阴影电路
公开(公告)号：US07278074B2
公开(公告)日：2007-10-02
申请号：US11044826
申请日：2005-01-26
申请人： Subhasish Mitra , Ming Zhang , Tak M. Mak , Quan Shi , Kee Sup Kim
发明人： Subhasish Mitra , Ming Zhang , Tak M. Mak , Quan Shi , Kee Sup Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.
摘要翻译：在一个实施例中，一种装置包括适于在第一输出端产生响应于数据输入信号和至少一个系统时钟信号的第一输出信号的系统电路; 阴影电路，其适于在第二输出端产生响应于所述数据输入信号和所述至少一个系统时钟信号的第二输出信号; 以及耦合到至少第一输出端子和第二输出端子的输出接合电路。

7. 发明授权

US07818642B2 Hierarchical test response compaction for a plurality of logic blocks 有权
标题翻译：多个逻辑块的分层测试响应压缩
公开(公告)号：US07818642B2
公开(公告)日：2010-10-19
申请号：US11903913
申请日：2007-09-25
申请人： Kee Sup Kim , Ming Zhang , Avi Kovacs
发明人： Kee Sup Kim , Ming Zhang , Avi Kovacs
IPC分类号： G01R31/3177 , G01R31/302
CPC分类号： G06F17/5068 , G01R31/318547
摘要： In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices has n input terminals and p output terminals, and the p output terminals of the second level matrices correspond to a compacted output from the multiple processor cores. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括第一级矩阵，每个包括m个输入端和n个输出端，每个输出端和耦合到处理器核心的第一级矩阵，以及分别耦合到第一级矩阵之一的n个输出端的第二级矩阵，的第二级矩阵具有n个输入端和p个输出端，并且第二级矩阵的p个输出端对应于来自多个处理器核的压缩输出。描述和要求保护其他实施例。

8. 发明申请

US20090083599A1 Hierarchical test response compaction for a plurality of logic blocks 有权
标题翻译：多个逻辑块的分层测试响应压缩
公开(公告)号：US20090083599A1
公开(公告)日：2009-03-26
申请号：US11903913
申请日：2007-09-25
申请人： Kee Sup Kim , Ming Zhang , Avi Kovacs
发明人： Kee Sup Kim , Ming Zhang , Avi Kovacs
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G06F17/5068 , G01R31/318547
摘要： In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices has n input terminals and p output terminals, and the p output terminals of the second level matrices correspond to a compacted output from the multiple processor cores. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括第一级矩阵，每个包括m个输入端和n个输出端，每个输出端和耦合到处理器核心的第一级矩阵，以及分别耦合到第一级矩阵之一的n个输出端的第二级矩阵，的第二级矩阵具有n个输入端和p个输出端，并且第二级矩阵的p个输出端对应于来自多个处理器核的压缩输出。描述和要求保护其他实施例。

9. 发明授权

US6076173A Architectural coverage measure 失效
标题翻译：建筑覆盖措施
公开(公告)号：US6076173A
公开(公告)日：2000-06-13
申请号：US1607
申请日：1997-12-31
申请人： Kee Sup Kim , Rathish Jayabharathi , Saviz Artang
发明人： Kee Sup Kim , Rathish Jayabharathi , Saviz Artang
IPC分类号： G01R31/3183 , G06F11/00
CPC分类号： G01R31/31835
摘要： A tractable architecture level coverage measure uses information about the coverage measures obtained by the data path blocks, control logic blocks and cache to obtain an overall measure of coverage. This technique is applicable to a variety of different designs using different fabrication processes. Moreover, it allows the use of extended length test vectors, for example, such as those using commercial software applications. Since the coverage measure does not rely on the traditional stuck at model, it is applicable to extended length test vectors that may be used with high performance systems.
摘要翻译：易处理的架构级覆盖测量使用关于由数据路径块，控制逻辑块和高速缓存获得的覆盖度量度的信息以获得覆盖的总体度量。该技术适用于使用不同制造工艺的各种不同设计。此外，它允许使用扩展长度测试向量，例如使用商业软件应用的测试向量。由于覆盖措施不依赖于传统的模型卡住，因此适用于可用于高性能系统的扩展长度测试向量。

10. 发明授权

US07185253B2 Compacting circuit responses 失效
标题翻译：压缩电路响应
公开(公告)号：US07185253B2
公开(公告)日：2007-02-27
申请号：US10107628
申请日：2002-03-27
申请人： Subhasish Mitra , Kee Sup Kim
发明人： Subhasish Mitra , Kee Sup Kim
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318566 , G01R31/3172 , G01R31/318547
摘要： Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.
摘要翻译：对于刺激的电路响应可能被压缩，使用压实器减少引脚数，而不增加电路元件的长度。根据本发明的一个实施例，可以在用于集成电路测试的扫描链中检测到错误。施加到输出引脚或其他连接器的输出的数量可以显着减少，从而节省成本。

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