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1. 发明授权

US06443628B1 Optical fiber connecting device, electronic equipment, network system and optical fiber connecting method 失效
标题翻译：光纤连接装置，电子设备，网络系统和光纤连接方法
公开(公告)号：US06443628B1
公开(公告)日：2002-09-03
申请号：US09469696
申请日：1999-12-22
申请人： Kazuyoshi Horie , Kuninori Shino , Kenichi Ookubo
发明人： Kazuyoshi Horie , Kuninori Shino , Kenichi Ookubo
IPC分类号： G02B638
CPC分类号： G02B6/382 , G02B6/243 , G02B6/3893
摘要： An optical fiber connecting method and apparatus in which optical communication is performed in a uni-core bidirectional system as optical crosstalk is prevented from occurring. To this end, an optical fiber connector 1 includes a refractive index matching member 2 and an optical fiber connecting unit 5. The refractive index matching member 2 has a refractive index substantially equivalent to that of the cores of optical fibers 101, 102. The optical fiber connecting unit 5 interconnects the optical fibers 101, 102 in a state in which end faces 101a, 102a of the optical fibers 101, 102 are contacted with a refractive index matching member 2 interposed between the end faces 101a, 102a of the optical fibers 101, 102.
摘要翻译：防止在单核双向系统中进行光通信作为光串扰的光纤连接方法和装置发生。为此，光纤连接器1包括折射率匹配构件2和光纤连接单元5.折射率匹配构件2具有与光纤101,102的芯的折射率基本相等的折射率。光学光纤连接单元5在光纤101,102的端面101a，102a与与光纤101的端面101a，102a之间插入的折射率匹配部件2接触的状态下将光纤101,102相互连接，102。

2. 发明授权

US06351584B1 Optical transmitter-receiver and optically sending/receiving method 有权
标题翻译：光收发器和光发送/接收方式
公开(公告)号：US06351584B1
公开(公告)日：2002-02-26
申请号：US09205982
申请日：1998-12-04
申请人： Kazuyoshi Horie , Yoichi Toriumi , Hideki Yoshida , Kenichi Ookubo , Kuninori Shino
发明人： Kazuyoshi Horie , Yoichi Toriumi , Hideki Yoshida , Kenichi Ookubo , Kuninori Shino
IPC分类号： G02B626
CPC分类号： G02B6/4246 , G02B6/4214 , G02B2006/4297
摘要： An optical transmitter-receiver according to the present invention is an optical transmitter-receiver connected to an optical fiber used for a single-core two-way optical communication channel for making a first optical signal S1 to be sent incident upon the end of the optical fiber and receiving a second optical signal S2 sent via the optical fiber. The above optical transmitter-receiver is provided with emission means for emitting a first optical signal S1, an optical system for making a first optical signal S1 from the emission means incident upon the incident end of the optical fiber in a direction R1 different from a direction in which a second optical signal S2 is outgoing from the end of the optical fiber and light receiving means for receiving a second optical signal S2 outgoing from the end of the optical fiber.
摘要翻译：根据本发明的光发射机 - 接收机是连接到用于单核双向光通信信道的光纤的光发射机 - 接收机，用于使第一光信号S1入射到光端并接收通过光纤发送的第二光信号S2。上述光发射机 - 接收机设置有用于发射第一光信号S1的发射装置，用于从沿光纤的入射端入射到发射装置的第一光信号S1沿与方向不同的方向R1 其中第二光信号S2从光纤的端部出射，以及用于接收从光纤末端出射的第二光信号S2的光接收装置。

3. 发明授权

US06693235B2 Key for musical instrument 有权
标题翻译：乐器钥匙
公开(公告)号：US06693235B2
公开(公告)日：2004-02-17
申请号：US10261603
申请日：2002-10-02
申请人： Kenichi Ookubo
发明人： Kenichi Ookubo
IPC分类号： G10C312
CPC分类号： G10C3/12
摘要： A key for a musical instrument is provided for effectively giving a touch load to the key, while employing an alternative material having a specific gravity equal to or larger than a predetermined value, instead of lead, as a material for the weight, simplifying works involved in fixing the weight in a key body, and reducing the frequency of troubles such as cracking of the key body, thereby reducing the manufacturing cost. The key comprises a swingable key body formed with an embedding hole which extends through a front plate in the vertical direction to reach the key body, and a weight made of an alternative material other than lead. The weight has a smooth portion and a knurled portion on the outer peripheral surface thereof. The weight is press-fitted into the embedding hole from the smooth portion and thereby fixed in the key body.
摘要翻译：提供一种用于乐器的钥匙，用于有效地给钥匙提供触摸负载，同时使用具有等于或大于预定值的比重的替代材料代替铅，作为重量的材料，简化工程在将重量固定在钥匙体中，并且减少诸如钥匙体的开裂的麻烦的频率，从而降低制造成本。该钥匙包括形成有嵌入孔的可摆动键体，该嵌入孔在垂直方向上延伸穿过前板，以到达键体，以及由除铅以外的替代材料制成的重量。该重量在其外周面上具有平滑部分和滚花部分。重量从平滑部分压入嵌入孔中，从而固定在钥匙体内。

4. 发明授权

US07009259B2 Semiconductor device and method of fabricating same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07009259B2
公开(公告)日：2006-03-07
申请号：US11100440
申请日：2005-04-07
申请人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
发明人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
IPC分类号： H01L31/119
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0922
摘要： A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.
摘要翻译：根据本发明的半导体器件（100）包括具有高介电强度的垂直PNP双极晶体管（20），NMOS晶体管（50）和PMOS晶体管（60），以及P型半导体衬底1，如图所示。 2 。同时形成PNP双极晶体管（20）的衬底隔离层（21），NMOS晶体管（50）的漏埋层（51）和PMOS晶体管（60）的背栅掩埋层（61）通过在半导体衬底（1）中选择性地注入诸如磷的N型杂质。本发明大大有助于减少制造BiCMOS IC等的工艺，其中包括具有容易控制的性能特征的垂直双极晶体管，例如电流放大因子，以及具有高介电强度的MOS晶体管，并且使得这种IC的更小型化成为可能。

5. 发明申请

US20050230762A1 Semiconductor device and method of fabricating same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050230762A1
公开(公告)日：2005-10-20
申请号：US11100590
申请日：2005-04-07
申请人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
发明人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
IPC分类号： H01L21/8222 , H01L21/8228 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L27/092 , H01L31/119
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0922
摘要： A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.
摘要翻译：根据本发明的半导体器件（100）包括具有高介电强度的垂直PNP双极晶体管（20），NMOS晶体管（50）和PMOS晶体管（60），以及P型半导体衬底1，如图1所示。 2。同时形成PNP双极晶体管（20）的衬底隔离层（21），NMOS晶体管（50）的漏埋层（51）和PMOS晶体管（60）的背栅掩埋层（61）通过在半导体衬底（1）中选择性地注入诸如磷的N型杂质。本发明大大有助于减少制造BiCMOS IC等的工艺，其中包括具有容易控制的性能特征的垂直双极晶体管，例如电流放大因子，以及具有高介电强度的MOS晶体管，并且使得这种IC的更小型化成为可能。

6. 发明授权

US06903424B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06903424B2
公开(公告)日：2005-06-07
申请号：US10474125
申请日：2003-02-03
申请人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
发明人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
IPC分类号： H01L21/8222 , H01L21/8228 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L27/092 , H01L31/119
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0922
摘要： A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.
摘要翻译：根据本发明的半导体器件（100）包括具有高介电强度的垂直PNP双极晶体管（20），NMOS晶体管（50）和PMOS晶体管（60），以及P型半导体衬底1，如图1所示。 2。同时形成PNP双极晶体管（20）的衬底隔离层（21），NMOS晶体管（50）的漏埋层（51）和PMOS晶体管（60）的背栅掩埋层（61）通过在半导体衬底（1）中选择性地注入诸如磷的N型杂质。本发明大大有助于减少制造BiCMOS IC等的工艺，其中包括具有容易控制的性能特征的垂直双极晶体管，例如电流放大因子，以及具有高介电强度的MOS晶体管，并且使得这种IC的更小型化成为可能。

7. 发明授权

US07015551B2 Semiconductor device and method of fabricating same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07015551B2
公开(公告)日：2006-03-21
申请号：US11100590
申请日：2005-04-07
申请人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
发明人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
IPC分类号： H01L31/119
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0922
摘要： A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.
摘要翻译：根据本发明的半导体器件（100）包括具有高介电强度的垂直PNP双极晶体管（20），NMOS晶体管（50）和PMOS晶体管（60），以及P型半导体衬底1，如图1所示。 2。同时形成PNP双极晶体管（20）的衬底隔离层（21），NMOS晶体管（50）的漏埋层（51）和PMOS晶体管（60）的背栅掩埋层（61）通过在半导体衬底（1）中选择性地注入诸如磷的N型杂质。本发明大大有助于减少制造BiCMOS IC等的工艺，其中包括具有容易控制的性能特征的垂直双极晶体管，例如电流放大因子，以及具有高介电强度的MOS晶体管，并且使得这种IC的更小型化成为可能。

8. 发明申请

US20050202623A1 Semiconductor device and method of fabricating same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050202623A1
公开(公告)日：2005-09-15
申请号：US11100440
申请日：2005-04-07
申请人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
发明人： Kenichi Ookubo , Hideki Mori , Shigeru Kanematsu
IPC分类号： H01L21/8222 , H01L21/8228 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L27/092 , H01L31/119 , H01L21/8238
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0922
摘要： A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.
摘要翻译：根据本发明的半导体器件（100）包括具有高介电强度的垂直PNP双极晶体管（20），NMOS晶体管（50）和PMOS晶体管（60），以及P型半导体衬底1，如图1所示。 PNP双极晶体管（20）的衬底隔离层（21），NMOS晶体管（50）的漏极埋层（51）和PMOS晶体管（60）的背栅极埋层（61）通过在半导体衬底（1）中选择性地注入N型杂质（例如磷）而同时形成。本发明大大有助于减少制造BiCMOS IC等的工艺，其中包括具有容易控制的性能特征的垂直双极晶体管，例如电流放大因子，以及具有高介电强度的MOS晶体管，并且使得这种IC的更小型化成为可能。

9. 发明授权

US06774294B2 Key for musical instrument 失效
标题翻译：乐器钥匙
公开(公告)号：US06774294B2
公开(公告)日：2004-08-10
申请号：US10201283
申请日：2002-07-24
申请人： Hidenori Kugimoto , Jun Ishii , Kenichi Ookubo
发明人： Hidenori Kugimoto , Jun Ishii , Kenichi Ookubo
IPC分类号： G10C312
CPC分类号： G10C3/12
摘要： A key for a musical instrument is provided for facilitating the attachment of a weight, and adjustments of a touch load, while using an alternative material for substitution for lead as a material for the weight. The key comprises a swingable key body formed with embedding holes, and weights each made of a material other than lead and having a threaded outer peripheral surface. The weight is screwed into the embedding hole for removable fit into the key body to give a load to the key body. A plurality of types of weights different in load from one another are provided for selecting one having an appropriate load therefrom to adjust the touch load.
摘要翻译：提供乐器的一个关键是为了便于重量的附着和触摸负载的调整，同时使用替代材料来代替铅作为重量的材料。钥匙包括形成有嵌入孔的可摆动钥匙主体，并且每个由除了引线之外的材料制成并具有螺纹外周表面的重量。重量被拧入嵌入孔中以便可拆卸地装配到钥匙体中，从而给钥匙体加载。提供了彼此负载不同的多种类型的重量，用于选择具有适当负载的重量以调节触摸负载。

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