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    • 5. 发明授权
    • Monolithic type varistor
    • 单片类型变量
    • US5119062A
    • 1992-06-02
    • US615369
    • 1990-11-19
    • Kazutaka NakamuraHiroaki TairaTohru HigashiAkinori NakayamaYasunobu YonedaYukio Sakabe
    • Kazutaka NakamuraHiroaki TairaTohru HigashiAkinori NakayamaYasunobu YonedaYukio Sakabe
    • H01C7/10
    • H01C7/10
    • A monolithic type varistor in which a plurality of inner electrodes are arranged in a sintered body composed of semiconductor ceramics so as to be overlapped with each other while being separated by semiconductor ceramic layers. The plurality of inner electrodes are electrically connected to first and second outer electrodes formed on both end surfaces of the sintered body. One or more non-connected type inner electrodes are arranged between adjacent ones of the plurality of inner electrodes and are not electrically connected to the outer electrodes, each of the non-connected type inner electrodes being spaced apart from each adjacent inner electrode or non-connected type inner electrode while being separated therefrom by a semiconductor ceramic layer. Voltage non-linearity is obtained by Schottky barriers formed at the interface of the inner electrode and the semiconductor ceramic layer and the interface of the non-connected type inner electrode and the semiconductor ceramic layer. The value of the number of grain boundaries between semiconductor particles in at least one semiconductor ceramic layer is two or less.
    • 一种单片型压敏电阻,其中多个内部电极被布置在由半导体陶瓷组成的烧结体中,以便在被半导体陶瓷层分离的同时彼此重叠。 多个内部电极电连接到形成在烧结体的两个端面上的第一和第二外部电极。 一个或多个非连接型内部电极布置在多个内部电极的相邻的内部电极之间,并且不与外部电极电连接,每个非连接型内部电极与每个相邻的内部电极或非电连接的内部电极间隔开, 连接型内部电极,同时由半导体陶瓷层分离。 通过在内部电极和半导体陶瓷层的界面处形成的肖特基势垒以及非连接型内部电极和半导体陶瓷层的界面获得电压非线性。 至少一个半导体陶瓷层中的半导体粒子之间的晶界数的值为2以下。