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1. 发明授权

US4507728A Data processing system for parallel processing of different instructions 失效
标题翻译：用于并行处理不同指令的数据处理系统
公开(公告)号：US4507728A
公开(公告)日：1985-03-26
申请号：US356468
申请日：1982-03-09
申请人： Kazushi Sakamoto , Tetsuro Okamoto , Shigeaki Okutani
发明人： Kazushi Sakamoto , Tetsuro Okamoto , Shigeaki Okutani
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8076 , G06F9/30 , G06F9/3885
摘要： The present invention is a data processing system which has plural operation units which can execute plural instructions in parallel. The system also has plural instruction control units each of which comprises at least two stages, one for reading source operands from a local storage, and another for writing a resultant operand into the local storage. Each instruction control unit is provided with specific bank timing signals for accessing the local storage.
摘要翻译：本发明是一种数据处理系统，其具有可并行执行多个指令的多个操作单元。该系统还具有多个指令控制单元，每个指令控制单元包括至少两个级，一个用于从本地存储器读取源操作数，另一级用于将合成的操作数写入本地存储器。每个指令控制单元被提供有用于访问本地存储器的特定存储体定时信号。

2. 发明授权

US4435765A Bank interleaved vector processor having a fixed relationship between start timing signals 失效
标题翻译：银行交错向量处理器在开始定时信号之间具有固定的关系
公开(公告)号：US4435765A
公开(公告)日：1984-03-06
申请号：US322717
申请日：1981-11-18
申请人： Keiichiro Uchida , Hiroshi Tamura , Tetsuro Okamoto , Shigeaki Okutani
发明人： Keiichiro Uchida , Hiroshi Tamura , Tetsuro Okamoto , Shigeaki Okutani
IPC分类号： G06F15/78 , G06F9/18
CPC分类号： G06F15/8076
摘要： The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.
摘要翻译：本发明公开了一种数据处理系统，其中在主存储器单元和操作处理单元之间提供由多个元件组成的多个向量寄存器，所需数据从主存储器单元传送到矢量寄存器并保持在其中，并且通过顺序访问所述向量寄存器内的元素来执行诸如逻辑操作的各种处理。本发明还包括多个存储体，其可以被独立地访问并被提供给矢量寄存器。每个向量寄存器的一系列元素在多个存储体中交错，并且在每个向量寄存器中具有相同编号的元件被布置在同一存储体中。为每一类处理指定开始访问所述向量寄存器的一系列元素所必需的定时，使得矢量操作处理可以非常有效地进行而不具有操作数冲突。

3. 发明授权

US4272827A Division processing method system having 2N-bit precision 失效
标题翻译：具有2N位精度的分割处理方法系统
公开(公告)号：US4272827A
公开(公告)日：1981-06-09
申请号：US21011
申请日：1979-03-16
申请人： Norio Inui , Noriaki Kume , Tetsuro Okamoto
发明人： Norio Inui , Noriaki Kume , Tetsuro Okamoto
IPC分类号： G06F7/52 , G06F7/527 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/5355
摘要： A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: ##EQU1## (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q.sub.1 +Q.sub.2 .times.2-n (Q.sub.1, Q.sub.2 : binary numbers). The binary numbers Q.sub.1 and Q.sub.2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q.sub.1 is used as a part of the data for performing the division processing of Q.sub.2, thus effectively transferring any error evolving during the processing of Q.sub.1 to Q.sub.2. The function is performed in a system having only four registers, each of N-bit capacity (precision), and an operation register, multiplication circuitry, division circuitry, and a shift circuit, affording proper control of data transfer between the registers.
摘要翻译：分割处理系统通过有效地使用N位精度的分割处理电路来执行2N位精度分割处理。系统以2N位精度进行除法，如下所示：（n = N：选定二进制数A，B，C和D中的位数）。上述表达式近似为Q1 + Q2x2-n（Q1，Q2：二进制数）的形式。二进制数Q1和Q2分别由具有N位精度的分割处理电路操作。通过有效控制，在Q1的分割处理期间引起的误差被用作执行Q2的分割处理的数据的一部分，从而有效地将在Q1处理期间发生的任何错误转移到Q2。该功能在仅具有四个寄存器，N位容量（精度）和操作寄存器，乘法电路，分频电路和移位电路的系统中执行，从而提供对寄存器之间的数据传输的适当控制。

4. 发明授权

US5499350A Vector data processing system with instruction synchronization 失效
标题翻译：带指令同步的矢量数据处理系统
公开(公告)号：US5499350A
公开(公告)日：1996-03-12
申请号：US469769
申请日：1995-06-06
申请人： Keiichiro Uchida , Tetsuro Okamoto
发明人： Keiichiro Uchida , Tetsuro Okamoto
IPC分类号： G06F9/38 , G06F15/00 , G06F15/16 , G06F15/78 , G06F17/10 , G06F17/16 , G06F9/30
CPC分类号： G06F9/3889 , G06F15/8061 , G06F9/30036 , G06F9/3836 , G06F9/3859 , G06F9/3877 , G06F9/3887
摘要： An information processing system including an arithmetic unit in which one unit of data is processed according to a corresponding one instruction, and another arithmetic unit in which a great amount of data are processed according to a corresponding instruction. Also included is an instruction controller which distributes instructions selectively to respective arithmetic units (12) and a main storage (12) which achieves two-way data communication with the arithmetic units. In the system synchronization is performed with respect to instructions, among the aforesaid instructions, which, above all, must be executed in respective fixed execution sequences, by utilizing a newly employed synchronization instruction. Further, the aforesaid instructions are classified, in dependence upon the execution sequence, into first instructions which are to be executed under a serial processing mode and second instructions which can be executed under a parallel processing mode, by inserting both a serialized-starting instruction (POST) and a serialized-releasing instruction into the aforesaid instructions.
摘要翻译：一种信息处理系统，包括其中根据相应的一个指令处理一个数据单元的运算单元，以及根据相应指令处理大量数据的另一运算单元。还包括指令控制器，其将选择性地分配给相应的算术单元（12）和实现与算术单元的双向数据通信的主存储器（12）。在系统中，通过利用新采用的同步指令，在上述指令中执行相对于指令的同步，首先必须在相应的固定执行序列中执行。此外，根据执行顺序将上述指令分类为在串行处理模式下执行的第一指令和可以在并行处理模式下执行的第二指令，通过插入串行启动指令（ POST）和序列化释放指令。

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