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1. 发明授权

US5149917A Wire conductor for harness 失效
标题翻译：线束导线
公开(公告)号：US5149917A
公开(公告)日：1992-09-22
申请号：US696503
申请日：1991-05-07
申请人： Kazuo Sawada , Atsuhiko Fujii , Yoshihiro Nakai , Naoyuki Ohkubo , Hajime Shiraishi , Fumio Ono , Katsushi Matsuda , Kazunori Tsuji
发明人： Kazuo Sawada , Atsuhiko Fujii , Yoshihiro Nakai , Naoyuki Ohkubo , Hajime Shiraishi , Fumio Ono , Katsushi Matsuda , Kazunori Tsuji
IPC分类号： B60R16/02 , C22C9/02 , C22F1/08 , H01B1/02
CPC分类号： B60R16/0215 , C22C9/02 , C22F1/08 , H01B1/026
摘要： Strands of a copper alloy containing 0.2 to 10 percent by weight of Sn are braided to form a stranded wire for a wire conductor for a harness having a conductor sectional area of 0.03 to 0.3 mm.sup.2. After the braiding, preferably stranded wire is heat treated so that its tensile strength is maintained at a prescribed level. The wire conductor for a harness has a breaking strength which is equivalent to that of a conventional harness wire, and is hardly broken by an impact. The wire conductor maintains its straightness, and strand ends do not fray upon cutting.

2. 发明授权

US5159689A Processing apparatus with functional hierarchical structure including selective operation of lower level units by higher level units 失效
标题翻译：具有功能分层结构的处理装置，包括由较高级别单元选择性地操作下级单元
公开(公告)号：US5159689A
公开(公告)日：1992-10-27
申请号：US434989
申请日：1989-11-13
申请人： Hajime Shiraishi
发明人： Hajime Shiraishi
IPC分类号： G06F9/30
CPC分类号： G06F9/30145
摘要： According to a processing apparatus with a hierarchical structure, a machine instruction has a hierarchical structure of a task level operation code, a control structure level operation code, an arithmetic level operation code and a low order level operation code, and accordingly an operation object field has a hierarchical structure of task level data, control condition data, arithmetic object data and low order level data. In correspondence with the hierarchical structure of the instruction, the processing apparatus has a hierarchical structure of task level functional blocks, control structure level functional blocks, arithmetic level functional blocks and low order level functional blocks. The functional blocks respectively have instruction decoders which are operated with serial or parallel processing.
摘要翻译：根据具有层次结构的处理装置，机器指令具有任务级操作代码，控制结构级操作代码，算术级操作代码和低级操作代码的分层结构，因此操作对象字段具有任务级数据，控制条件数据，算术对象数据和低级数据的分层结构。与指令的层次结构相对应，处理装置具有任务级功能块，控制结构级功能块，算术级功能块和低级功能块的层次结构。功能块分别具有通过串行或并行处理操作的指令解码器。

3. 发明授权

US5111388A Processing apparatus with functional hierarchical structure using corresponding hierarchical machine instruction fields 失效
标题翻译：具有功能分层结构的加工设备，使用相应的分层机器指导领域
公开(公告)号：US5111388A
公开(公告)日：1992-05-05
申请号：US434987
申请日：1989-11-13
申请人： Hajime Shiraishi
发明人： Hajime Shiraishi
IPC分类号： G06F9/30
CPC分类号： G06F9/30145
摘要： According to a processing apparatus with a hierarchical structure, a machine instruction has a hierarchical structure of a task level operation code, a control structure level operation code, an arithmetic level operation code and a low order level operation code, and accordingly an operation object field has a hierarchical structure of task level data, control condition data, arithmetic object data and low order level data. In correspondence with the hierarchical structure of the instruction, the processing apparatus has a hierarchical structure of task level functional blocks, control structure level functional blocks, arithmetic level functional blocks and low order level functional blocks. The functional blocks respectively have instruction decoders which are operated with serial or parallel processing.

4. 发明授权

US5867691A Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same 失效
标题翻译：在分层结构中排列的功能块与大规模集成电路之间同步系统
公开(公告)号：US5867691A
公开(公告)日：1999-02-02
申请号：US31363
申请日：1993-03-15
申请人： Hajime Shiraishi
发明人： Hajime Shiraishi
IPC分类号： H01L21/82 , G06F1/10 , G06F1/12 , G06F9/52 , G06F15/16 , G06F15/173 , G06F15/177 , G06F17/50 , H01L27/02
CPC分类号： H01L27/0207 , G06F1/10 , G06F1/12 , G06F17/5059
摘要： An inter-hierarchy synchronizing system and an LSI include a plurality of function blocks taking a hierarchical structure and having timing systems expressed by timing variables independent of each other and inter-hierarchy synchronizing blocks disposed these hierarchies. This synchronizing block has: an input event temporary storage part for receiving and storing an input event generation signal group from a higher-level block; an activation timing judging part for judging activations of a plurality of function blocks and transmitting activation signals; an output event temporary storage part for receiving and storing output event generation signals including a completion signal from lower-level blocks; and a final completion signal judging part for judging a final completion state on the basis of a signal from the output event temporary storage part and transmitting a final completion signal to the high-block. The pre-designed function blocks are operable at a high speed without undergoing an influence by a delay of clocks.
摘要翻译：层间同步系统和LSI包括采用层次结构并具有由彼此独立的定时变量表示的定时系统的多个功能块以及设置这些层次的层间同步块。该同步块具有：输入事件临时存储部分，用于从上级块接收和存储输入事件生成信号组; 激活定时判断部分，用于判断多个功能块的激活并发送激活信号; 输出事件临时存储部分，用于接收和存储包括来自下级块的完成信号的输出事件生成信号; 以及最终完成信号判断部分，用于基于来自输出事件临时存储部分的信号来判断最终完成状态，并将最终完成信号发送到高块。预先设计的功能块可以高速工作，而不受时钟延迟的影响。

5. 发明授权

US5208831A Network interface system 失效
标题翻译：网络接口系统
公开(公告)号：US5208831A
公开(公告)日：1993-05-04
申请号：US829534
申请日：1992-02-03
申请人： Masaji Ueno , Akihito Nishikawa , Shinichi Iida , Hajime Shiraishi
发明人： Masaji Ueno , Akihito Nishikawa , Shinichi Iida , Hajime Shiraishi
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： It is an object of this invention to provide a novel network interface system which is able to connect automatically to the respective network stations having different data transfer speeds, in order to avoid the above problems. According to this invention, there is provided a detector and a selector in the communication interface to automatically select the appropriate data transfer speed. In the above structure, the speed of communication data transferred by a network is one of two detected by the detector which is able to detect a transfer speed and provide outputs at a first level signal when the transfer speed is at one level and outputs a second level signal when it is at a second level. The selecting means selects the frequency to connect a network station in response to the signal output from the detector. As a result, users need not select the module by themselves, the system automatically select the module.
摘要翻译：本发明的目的是提供一种能够自动连接到具有不同数据传输速度的各个网络站的新型网络接口系统，以避免上述问题。根据本发明，在通信接口中提供了一个检测器和选择器，用于自动选择适当的数据传输速度。在上述结构中，由网络传送的通信数据的速度是检测器检测到的两种速度之一，当传输速度处于一个级别时，能够检测传送速度并提供第一级信号的输出，并输出第二级当它处于第二级时的电平信号。选择装置响应于从检测器输出的信号选择连接网络站的频率。因此，用户不需要自己选择模块，系统自动选择模块。

6. 发明授权

US4901225A Processing apparatus with hierarchical structure for implementing a machine instruction 失效
标题翻译：具有用于实现机器指令的分级结构的处理装置
公开(公告)号：US4901225A
公开(公告)日：1990-02-13
申请号：US720881
申请日：1985-04-08
申请人： Hajime Shiraishi
发明人： Hajime Shiraishi
IPC分类号： G06F9/30
CPC分类号： G06F9/30145
摘要： According to a processing apparatus with a hierarchical structure, a machine instruction has a hierarchical structure of a task level operation code, a control structure level operation code, an arithmetic level operation code and a low order level operation code, and accordingly an operation object field has a hierarchical structure of task level data, control condition data, arithmetic object data and low order level data. In correspondence with the hierarchical structure of the instruction, the processing apparatus has a hierarchical structure of task level functional blocks, control structure level functional blocks, arithmetic level functional blocks and low order level functional blocks. The functional blocks respectively have instruction decoders which are operated with serial or parallel processing.
摘要翻译：根据具有层次结构的处理装置，机器指令具有任务级操作代码，控制结构级操作代码，算术级操作代码和低级操作代码的分层结构，因此操作对象字段具有任务级数据，控制条件数据，算术对象数据和低级数据的分层结构。与指令的层次结构相对应，处理装置具有任务级功能块，控制结构级功能块，算术级功能块和低级功能块的层次结构。功能块分别具有通过串行或并行处理操作的指令解码器。

7. 发明授权

US5685006A Application specific integrated circuit having hierarchical structure and method of organizing such circuit using inheritance information 失效
标题翻译：专用集成电路具有分层结构和使用继承信息组织此类电路的方法
公开(公告)号：US5685006A
公开(公告)日：1997-11-04
申请号：US365009
申请日：1994-12-28
申请人： Hajime Shiraishi
发明人： Hajime Shiraishi
IPC分类号： G06F15/78 , G06F17/50 , G06F13/38 , G06F13/20
CPC分类号： G06F17/5045 , G06F15/7867 , G06F17/5068
摘要： An application specific integrated circuit which can develop a wide variety of integrated circuits in a short time period is provided. In respective functional blocks, inheritance circuits capable of holding and transferring function inheritance information necessary for univocally specifying functions of respective corresponding functional blocks, bearer switches serving as a data transfer switch, and program wiring mechanisms are provided. After a mother wafer on which such units are hierarchically connected by function inheritance information read-out buses is manufactured, function inheritance information is read out to obtain, on the basis of the read out information, information for connecting partial circuit groups within block having one-to-one correspondence with respect to that information to drive programmable wiring mechanisms by using such information, thus to obtain connections as defined be the system requirement specification.
摘要翻译：提供了可以在短时间内开发各种集成电路的专用集成电路。在各功能块中，提供能够保持和传送用于单独指定各个相应功能块的功能所必需的功能继承信息的继承电路，用作数据传送开关的承载开关和程序布线机构。在通过功能继承信息读出总线分层连接这样的单元的母晶片之后，读出功能继承信息，以根据读出的信息获得用于连接具有一个的块内的部分电路组的信息通过使用这种信息来驱动可编程布线机构，从而获得如系统要求规范所定义的连接。

8. 发明授权

US4641044A Clock generator with reset and initialization circuitry 失效
标题翻译：具有复位和初始化电路的时钟发生器
公开(公告)号：US4641044A
公开(公告)日：1987-02-03
申请号：US676318
申请日：1984-11-29
申请人： Hajime Shiraishi
发明人： Hajime Shiraishi
IPC分类号： H03K3/02 , G06F1/04 , H03K5/00 , H03K17/00 , H03K23/00 , H03K3/017
CPC分类号： G06F1/04
摘要： After detecting a leading edge of a stop control signal supplied from an external circuit, an oscillation output signal is cut off at an input side of a frequency divider in synchronism with the first leading edge of a clock signal generated from the frequency divider, thereby stopping the generation of clock signals. The stopping of the clock signal generating operation is released in such a manner that, immediately after a trailing edge of an external control signal is detected, an internal state of the frequency divider is initialized, and the oscillation output signal which has been cut off is supplied to the frequency divider again, thereby generating a proper clock signal.
摘要翻译：在检测到从外部电路提供的停止控制信号的前沿之后，在分频器的输入侧与从分频器产生的时钟信号的第一前沿同步地切断振荡输出信号，从而停止生成时钟信号。释放时钟信号产生操作的停止，使得在检测到外部控制信号的后沿之后，初始化分频器的内部状态，并且已经被切断的振荡输出信号是再次提供给分频器，从而产生适当的时钟信号。

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