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1. 发明授权

US08030956B2 Method of on-chip current measurement and semiconductor IC 失效
标题翻译：片上电流测量方法和半导体IC
公开(公告)号：US08030956B2
公开(公告)日：2011-10-04
申请号：US12878564
申请日：2010-09-09
申请人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/3187 , G01R31/28
CPC分类号： G01R19/0092 , Y10T307/406
摘要： A semiconductor integrated circuit that includes a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.
摘要翻译：一种半导体集成电路，包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据电流块的端子之间的电压来获得流向电路块的电流电源开关处于电源开关接通的状态和电源开关的导通电阻。因此，可以在芯片正常工作的状态下测量电路块的电流。

2. 发明授权

US07812628B2 Method of on-chip current measurement and semiconductor IC 失效
标题翻译：片上电流测量方法和半导体IC
公开(公告)号：US07812628B2
公开(公告)日：2010-10-12
申请号：US11956122
申请日：2007-12-13
申请人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/26
CPC分类号： G01R19/0092 , Y10T307/406
摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.
摘要翻译：半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流电源开关处于电源开关接通的状态和电源开关的导通电阻。基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。因此，可以在芯片正常工作的状态下测量电路块的电流。

3. 发明申请

US20110006792A1 METHOD OF ON-CHIP CURRENT MEASUREMENT AND SEMICONDUCTOR IC 失效
标题翻译：片上电流测量方法和半导体IC
公开(公告)号：US20110006792A1
公开(公告)日：2011-01-13
申请号：US12878564
申请日：2010-09-09
申请人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/3187
CPC分类号： G01R19/0092 , Y10T307/406
摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.
摘要翻译：半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流电源开关处于电源开关接通的状态和电源开关的导通电阻。基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。因此，可以在芯片正常工作的状态下测量电路块的电流。

4. 发明授权

US07954023B2 Semiconductor integrated circuit including power domains 有权
标题翻译：半导体集成电路包括电源域
公开(公告)号：US07954023B2
公开(公告)日：2011-05-31
申请号：US12342015
申请日：2008-12-22
申请人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/28
CPC分类号： H03K19/0016
摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.
摘要翻译：提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN）电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

5. 发明申请

US20090160544A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090160544A1
公开(公告)日：2009-06-25
申请号：US12342015
申请日：2008-12-22
申请人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
IPC分类号： H01L25/00
CPC分类号： H03K19/0016
摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.
摘要翻译：提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN）电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

6. 发明授权

US08248099B2 Semiconductor integrated circuit and circuit operation method 失效
标题翻译：半导体集成电路和电路操作方法
公开(公告)号：US08248099B2
公开(公告)日：2012-08-21
申请号：US12787090
申请日：2010-05-25
申请人： Kazuo Otsuga , Yusuke Kanno
发明人： Kazuo Otsuga , Yusuke Kanno
IPC分类号： G01R31/28
CPC分类号： G01R31/31721
摘要： In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor. When the result data detected indicates the fast state, the power supply voltage VDD is set to a lower power supply voltage level “VDD−ΔVDD” corresponding to a small variation gradient “β[V/σ]”. When the result data detected indicates the typical state, the power supply voltage VDD is set to an intermediate power supply voltage level “VDD±0”. When the result data detected indicates the slow state, the power supply voltage VDD is set to a higher power supply voltage level “VDD+ΔVDD” corresponding to a large variation gradient “α[V/σ]”.
摘要翻译：在其中低阈值电压和高阈值电压晶体管被混合地布置的半导体集成电路中，通过调节电源电压VDD可以在速度控制执行中适当地控制每个晶体管的工作速度。半导体集成电路包括内部电路和测量电路。内部电路包括低阈值电压MOS晶体管和高阈值电压MOS晶体管，并且低阈值电压MOS晶体管的阈值电压变化程度大于高阈值电压MOS晶体管的阈值电压变化的程度阈值电压MOS晶体管。测量电路检测低阈值电压MOS晶体管和高阈值电压MOS晶体管中的哪一个快速，典型和慢速状态。当检测到的结果数据指示快速状态时，电源电压VDD被设置为对应于小变化梯度“＆bgr; [V /＆sgr]]的较低电源电压电平”VDD-＆Dgr; VDD“。当检测到的结果数据表示典型状态时，将电源电压VDD设定为中间电源电压电平“VDD±0”。当检测到的结果数据表示慢速状态时，将电源电压VDD设定为与较大变化梯度“α[V /＆sgr”]对应的较高电源电压电平“VDD +＆Dgr; VDD”。

7. 发明授权

US08339190B2 Semiconductor integrated circuit and electronic device 有权
标题翻译：半导体集成电路和电子设备
公开(公告)号：US08339190B2
公开(公告)日：2012-12-25
申请号：US13012881
申请日：2011-01-25
申请人： Kazuo Otsuga , Yusuke Kanno , Yoshio Takazawa
发明人： Kazuo Otsuga , Yusuke Kanno , Yoshio Takazawa
IPC分类号： G05F1/10
CPC分类号： G01R31/31725 , G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.
摘要翻译： AVS（自适应电压调节）技术，其中考虑了变异性和不确定性。在安排AVS技术的系统中，设置对于每种类型的处理变化最佳的检测电路。如此布置的检测电路的示例包括用于检测相对于门延迟平均值的相对值的可变性的第一测量电路和用于检测不确定性的第二测量电路，其产生与门相关的相对值延迟标准偏差。第一和第二测量电路彼此分开设置。用于决定电源电压的控制信息是根据检测电路产生的相对值来准备的。在准备控制信息时，一个表数据。

8. 发明授权

US07994822B2 Semiconductor device for synchronous communication between stacked LSI 有权
标题翻译：用于堆叠LSI之间的同步通信的半导体器件
公开(公告)号：US07994822B2
公开(公告)日：2011-08-09
申请号：US12690659
申请日：2010-01-20
申请人： Kazuo Otsuga , Kenichi Osada , Makoto Saen
发明人： Kazuo Otsuga , Kenichi Osada , Makoto Saen
IPC分类号： H03K19/00
CPC分类号： H03L7/0812 , G06F1/12 , H01L25/18 , H01L2224/48137 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H03K5/15033 , H03L7/07
摘要： The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.
摘要翻译：通过在堆叠的计算LSI之间同步通信和计算，可以提高整个系统的性能。堆叠的外部通信LSI和计算LSI中的每一个具有将晶体振荡器时钟信号相乘的PLL，分配时钟信号的时钟脉冲发生器和触发器电路。计算LSI具有由时钟相位比较器，延迟控制器和延迟链组成的DLL电路。为了同步外部通信LSI和计算LSI的通信和计算，同步参考时钟信号从外部通信LSI经由通孔发送到计算LSI。计算LSI的内部时钟信号与来自外部通信LSI的同步基准时钟信号通过DLL电路同步。

9. 发明申请

US20100182046A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100182046A1
公开(公告)日：2010-07-22
申请号：US12690659
申请日：2010-01-20
申请人： Kazuo Otsuga , Kenichi Osada , Makoto Saen
发明人： Kazuo Otsuga , Kenichi Osada , Makoto Saen
IPC分类号： H03K19/00
CPC分类号： H03L7/0812 , G06F1/12 , H01L25/18 , H01L2224/48137 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H03K5/15033 , H03L7/07
摘要： The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.
摘要翻译：通过在堆叠的计算LSI之间同步通信和计算，可以提高整个系统的性能。堆叠的外部通信LSI和计算LSI中的每一个具有将晶体振荡器时钟信号相乘的PLL，分配时钟信号的时钟脉冲发生器和触发器电路。计算LSI具有由时钟相位比较器，延迟控制器和延迟链组成的DLL电路。为了同步外部通信LSI和计算LSI的通信和计算，同步参考时钟信号从外部通信LSI经由通孔发送到计算LSI。计算LSI的内部时钟信号与来自外部通信LSI的同步基准时钟信号通过DLL电路同步。

10. 发明授权

US07323741B2 Semiconductor nonvolatile memory device 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US07323741B2
公开(公告)日：2008-01-29
申请号：US10998630
申请日：2004-11-30
申请人： Kazuo Otsuga , Hideaki Kurata , Yoshitaka Sasago
发明人： Kazuo Otsuga , Hideaki Kurata , Yoshitaka Sasago
IPC分类号： H01L29/788 , H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7885 , G11C11/5621 , G11C16/0433 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42328
摘要： A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.
摘要翻译：能够使用反转层作为布线的能够进行高速编程的低成本半导体非易失性存储器件以及该器件的制造方法。半导体存储器件包括在源极和漏极区域之间并与之平行的位置处的辅助电极，并且与相互平行形成的源极区域和漏极区域没有位置重叠; 其中用于热电子源注入的辅助电极用作编程（写入）的辅助电极; 并且在读取操作期间，在辅助电极下形成的反型层用作源极区域或漏极区域。

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