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1. 发明授权

US07922843B2 Method and system for laminating optical elements 有权
公开(公告)号：US07922843B2
公开(公告)日：2011-04-12
申请号：US12422907
申请日：2009-04-13
申请人： Kazuo Kitada , Yoshihiro Kameda , Kanji Nishida , Tomokazu Yura , Takaichi Amano , Hiromichi Ohashi , Atsushi Hino , Naoyuki Matsuo
发明人： Kazuo Kitada , Yoshihiro Kameda , Kanji Nishida , Tomokazu Yura , Takaichi Amano , Hiromichi Ohashi , Atsushi Hino , Naoyuki Matsuo
IPC分类号： B32B41/00
CPC分类号： G02F1/133305 , B23K26/0846 , B23K26/40 , B23K2101/16 , B23K2103/172 , B29D11/0073 , B32B37/182 , B32B38/0004 , B32B38/10 , B32B41/00 , B32B2041/04 , B32B2305/55 , B32B2307/40 , B32B2307/42 , B32B2310/0843 , B32B2457/202 , G01N21/8422 , G02B5/3016 , G02F1/1303 , G02F1/133528 , Y10T156/1056 , Y10T156/1057 , Y10T156/12
摘要： A strip-shaped polarizing film has a protective film strip conformably adhered to one surface thereof and a releasable liner conformably adhered to the other surface thereof and delivered from a film delivering station 1. After an appearance inspection, a lamination of the protective film strip and the polarizing film strip F is half-cut using a laser unit 11 to form an array of laminations each consisting of a protective film and a polarizing film F, with the releasable liner being left intact. Then, the polarizing films F are fed to a peeling mechanism 4. The peeling mechanism 4 feeds a forwardmost one the polarizing films F to a laminating mechanism 5 while peeling off the releasable liner therefrom by a knife-edged member. The forwardmost polarizing film F is laminated to a liquid-crystal panel W conveyed to the laminating mechanism by a panel transport apparatus 18 in synchronization of the feeding of the forwardmost polarizing film F.

2. 发明授权

US07913734B2 Method and system for laminating optical elements 有权
标题翻译：光学元件层压方法及系统
公开(公告)号：US07913734B2
公开(公告)日：2011-03-29
申请号：US12843430
申请日：2010-07-26
申请人： Kazuo Kitada , Yoshihiro Kameda , Kanji Nishida , Tomokazu Yura , Takaichi Amano , Hiromichi Ohashi , Atsushi Hino , Naoyuki Matsuo
发明人： Kazuo Kitada , Yoshihiro Kameda , Kanji Nishida , Tomokazu Yura , Takaichi Amano , Hiromichi Ohashi , Atsushi Hino , Naoyuki Matsuo
IPC分类号： B32B41/00
CPC分类号： G02F1/133305 , B23K26/0846 , B23K26/40 , B23K2101/16 , B23K2103/172 , B29D11/0073 , B32B37/182 , B32B38/0004 , B32B38/10 , B32B41/00 , B32B2041/04 , B32B2305/55 , B32B2307/40 , B32B2307/42 , B32B2310/0843 , B32B2457/202 , G01N21/8422 , G02B5/3016 , G02F1/1303 , G02F1/133528 , Y10T156/1056 , Y10T156/1057 , Y10T156/12
摘要： A strip-shaped polarizing film has a protective film strip conformably adhered to one surface thereof and a releasable liner conformably adhered to the other surface thereof and delivered from a film delivering station 1. After an appearance inspection, a lamination of the protective film strip and the polarizing film strip F is half-cut using a laser unit 11 to form an array of laminations each consisting of a protective film and a polarizing film F, with the releasable liner being left intact. Then, the polarizing films F are fed to a peeling mechanism 4. The peeling mechanism 4 feeds a forwardmost one the polarizing films F to a laminating mechanism 5 while peeling off the releasable liner therefrom by a knife-edged member. The forwardmost polarizing film F is laminated to a liquid-crystal panel W conveyed to the laminating mechanism by a panel transport apparatus 18 in synchronization of the feeding of the forwardmost polarizing film F.
摘要翻译：带状偏振膜具有与其一个表面一致地粘附的保护膜条，并且可剥离衬垫顺应地粘附到其另一表面并从膜输送站1输送。在外观检查之后，将保护膜条和使用激光单元11对偏光膜条F进行半切割，以形成每个由保护膜和偏振膜F组成的叠片阵列，其中可释放的衬垫保持不变。然后，将偏光膜F供给到剥离机构4.剥离机构4将偏光膜F的最前面的一个将切割薄膜F的层叠机构5向刀片边缘部件剥离。最前面的偏振片F与最前方的偏振片F的馈送同步地层叠到通过面板传送装置18输送到层叠机构的液晶面板W.

3. 发明授权

US08351224B2 Power conversion apparatus 有权
标题翻译：电力转换装置
公开(公告)号：US08351224B2
公开(公告)日：2013-01-08
申请号：US12506535
申请日：2009-07-21
申请人： Hiromichi Ohashi , Kyungmin Sung , Masamu Kamaga , Mitsuaki Shimizu
发明人： Hiromichi Ohashi , Kyungmin Sung , Masamu Kamaga , Mitsuaki Shimizu
IPC分类号： H02M5/45 , H02J3/00
CPC分类号： H02M5/4585 , H02M5/271
摘要： A power conversion apparatus includes a main circuit with switches, and performs power conversion to generate power to a three-phase AC load from a three- or single-phase AC power supply. Some of the switches are configured, using a bidirectional switch including a normally-on device that is turned OFF when a gate circuit is provided with a positive or negative voltage, and a normally-off device that is turned ON when the gate circuit is provided with a positive or negative voltage, to provide only a specific unidirectional current flow when the gate circuit is not activated, and when the gate circuit is activated, provide and control a bidirectional current flow to direct only in an arbitrary unidirectional way. By providing the power conversion apparatus with a capability of directing back, to a load (motor), any power coming therefrom, the conversion apparatus requires no direct-current link capacitor and a diode clamping circuit.
摘要翻译：电力转换装置包括具有开关的主电路，并且进行电力转换以从三相或单相交流电源向三相交流负载产生电力。一些开关被配置为使用包括在门电路被提供正或负电压时被关断的常开装置的双向开关和当提供门电路时被接通的常关装置具有正或负电压，仅在门电路未激活时仅提供特定的单向电流，并且当门电路被激活时，提供和控制双向电流仅以任意的单向方式引导。通过为电力转换装置提供向负载（电动机）提供来自其的任何电力的能力，转换装置不需要直流链路电容器和二极管钳位电路。

4. 发明授权

US07238576B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07238576B2
公开(公告)日：2007-07-03
申请号：US10403122
申请日：2003-04-01
申请人： Masakazu Yamaguchi , Ichiro Omura , Wataru Saito , Takashi Shinohe , Hiromichi Ohashi
发明人： Masakazu Yamaguchi , Ichiro Omura , Wataru Saito , Takashi Shinohe , Hiromichi Ohashi
IPC分类号： H01L21/336
CPC分类号： H01L29/7803 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/66712 , H01L29/7722 , H01L29/7802 , H01L29/7805 , H01L29/7811 , H01L29/7813 , H01L29/7824
摘要： A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity type on a surface of the drift layer of first conductivity type, a source layer of first conductivity type selectively provided on a surface of the first base layer of second conductivity type, a gate insulating film on the first base layer of second conductivity type between the source layer and the drift layer, a gate electrode on the gate insulating film, a second base layer of second conductivity type on a surface of the drift layer, a first main electrode on the drain layer, and a second main electrode on the source layer, the first base layer and the second base layer.
摘要翻译：半导体器件包括第一导电类型的漏极层，漏极层上的第一和第二导电类型的漂移层，漂移层之间的绝缘膜和与漂移层接触的第二导电类型的第一基底层，第一导电类型的漂移层，选择性地设置在第二导电类型的第一基极层的表面上的第一导电类型的源极层，在源极层和漂移体之间的第二导电类型的第一基极层上的栅极绝缘膜栅极绝缘膜上的栅电极，漂移层的表面上的第二导电类型的第二基极层，漏极层上的第一主电极和源极层上的第二主电极，第一基极层和第二基层。

5. 发明申请

US20050087765A1 Power semiconductor device used for power control 失效
标题翻译：功率半导体器件用于功率控制
公开(公告)号：US20050087765A1
公开(公告)日：2005-04-28
申请号：US10986103
申请日：2004-11-12
申请人： Wataru Saito , Ichiro Omura , Hiromichi Ohashi
发明人： Wataru Saito , Ichiro Omura , Hiromichi Ohashi
IPC分类号： H01L29/812 , H01L21/338 , H01L27/06 , H01L29/778 , H01L31/0336
CPC分类号： H01L27/0605 , H01L29/0619 , H01L29/0657 , H01L29/1602 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/7787 , H01L29/872
摘要： A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semi-conductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.
摘要翻译：功率半导体器件包括第一半导体层，第一导电类型的第二半导体层，第一和第二主电极，控制电极和第三半导体层。第二半导体层形成在第一半导体层上。第一和第二主电极彼此分开地形成在第二半导体层上。控制电极形成在第一和第二主电极之间的第二半导体层上。在控制电极和第二主电极之间的第二半导体层上形成第三半导体层。

6. 发明授权

US5780887A Conductivity modulated MOSFET 失效
公开(公告)号：US5780887A
公开(公告)日：1998-07-14
申请号：US261254
申请日：1994-06-14
申请人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
发明人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/739 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0696 , H01L29/7393 , H01L29/7395
摘要： A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

7. 发明授权

US5714775A Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US5714775A
公开(公告)日：1998-02-03
申请号：US633688
申请日：1996-04-19
申请人： Tomoki Inoue , Ichiro Omura , Hiromichi Ohashi
发明人： Tomoki Inoue , Ichiro Omura , Hiromichi Ohashi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/32 , H01L29/739 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/1095 , H01L29/32
摘要： A p-type emitter layer having a low resistivity is arranged on a bottom surface of an n-type base layer having a high resistivity. A p-type base layer is formed in a top surface of the n-type base layer. Trenches are formed in the p-type base layer and the n-type base layer such that each trench penetrates the p-type base layer and reaches down to a halfway depth in the n-type base layer. Inter-trench regions made of semiconductor are defined between the trenches. An n-type emitter layer having a low resistivity is formed in a surface of the p-type base layer to be in contact with the upper part of each trench. A gate electrode is buried via a gate insulating film in each trench. That side surface of each inter-trench region which faces the gate electrode consists of a {100} plane.
摘要翻译：具有低电阻率的p型发射极层布置在具有高电阻率的n型基极层的底表面上。 p型基底层形成在n型基底层的顶表面上。在p型基底层和n型基底层中形成沟槽，使得每个沟槽穿过p型基底层并在n型基底层中下降到中间深度。在沟槽之间限定由半导体制成的沟槽间区域。在p型基底层的表面上形成具有低电阻率的n型发射极层，以与每个沟槽的上部接触。每个沟槽中的栅极绝缘膜埋入栅电极。面对栅电极的每个沟槽间区域的侧表面由{100}平面组成。

8. 发明授权

US5093701A Conductivity modulated MOSFET 失效
公开(公告)号：US5093701A
公开(公告)日：1992-03-03
申请号：US146405
申请日：1988-01-21
申请人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
发明人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/739
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0696 , H01L29/7393 , H01L29/7395
摘要： A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

9. 发明授权

US5006921A Power semiconductor switching apparatus with heat sinks 失效
标题翻译：功率半导体开关设备带散热片
公开(公告)号：US5006921A
公开(公告)日：1991-04-09
申请号：US331288
申请日：1989-03-31
申请人： Masaru Ishizuka , Yasuyuki Yokono , Asako Matsuura , Yoshio Kamei , Hiromichi Ohashi , Mitsuhiko Kitagawa , Tomiya Sasaki , Shigeki Monma
发明人： Masaru Ishizuka , Yasuyuki Yokono , Asako Matsuura , Yoshio Kamei , Hiromichi Ohashi , Mitsuhiko Kitagawa , Tomiya Sasaki , Shigeki Monma
IPC分类号： H01L23/473 , H01L25/07
CPC分类号： H01L23/4735 , H01L24/33 , H01L25/072 , H01L2924/01322 , H01L2924/1301 , H01L2924/13055 , H01L2924/13091 , H01L2924/351
摘要： A semiconductor switching apparatus includes a member for radiating heat generated from semiconductor switching element chips and for reducing a thermal stress. The lengths of gate electrode wires are equally set. The semiconductor switching apparatus has a large capacity and good switching characteristics.
摘要翻译：半导体开关装置包括用于散发由半导体开关元件芯片产生的热量并减少热应力的构件。栅极电极线的长度同样设定。半导体开关装置具有大容量和良好的开关特性。

10. 发明授权

US4700466A Method of manufacturing semiconductor device wherein silicon substrates are bonded together 失效
标题翻译：制造半导体器件的方法，其中硅衬底结合在一起
公开(公告)号：US4700466A
公开(公告)日：1987-10-20
申请号：US825544
申请日：1986-02-03
申请人： Akio Nakagawa , Hiromichi Ohashi , Tsuneo Ogura , Masaru Shimbo
发明人： Akio Nakagawa , Hiromichi Ohashi , Tsuneo Ogura , Masaru Shimbo
IPC分类号： H01L29/78 , H01L21/02 , H01L21/18 , H01L21/20 , H01L21/306 , H01L21/336 , H01L27/12 , H01L29/74 , H01L29/861 , H01L21/461
CPC分类号： H01L21/02052 , H01L21/187
摘要： A method of manufacturing a semiconductor device, wherein a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer is formed. A first silicon substrate, having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, is brought into contact with a second silicon substrate which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other. The contacting substrates are then placed in a clean atmosphere so that virtually no foreign substances are present therebetween, and annealed at a temperature of not less than 200.degree. C. so as to bond them together, thereby forming the second impurity-doped layer consisting of the third impurity doped layer and the second silicon substrate.
摘要翻译：一种制造半导体器件的方法，其中形成具有第一杂质掺杂层和杂质浓度高于第一杂质掺杂层的第二杂质掺杂层的半导体晶片。具有第一杂质掺杂层和第三杂质掺杂层的第一硅衬底，其具有比第一杂质掺杂层高的杂质浓度和与第二杂质掺杂层相同的导电类型，以及其表面经镜面抛光与第二硅衬底接触，第二硅衬底的杂质浓度高于第一杂质掺杂层的杂质浓度并且具有与第二杂质掺杂层相同的导电类型，并且其表面为镜面抛光，使得其镜面抛光表面彼此接触。然后将接触的基材放置在清洁的气氛中，实际上不存在异物，并在不低于200℃的温度下进行退火，以将它们结合在一起，由此形成第二杂质掺杂层，由第三杂质掺杂层和第二硅衬底。

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