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1. 发明授权

US5811996A Gate drive circuit having reduced current-consumption and rapid inductive energy dissipation 失效
标题翻译：栅极驱动电路具有降低的电流消耗和快速的感应能量耗散
公开(公告)号：US5811996A
公开(公告)日：1998-09-22
申请号：US767952
申请日：1996-12-17
申请人： Kazunori Oyabe , Tatsuhiko Fujihira , Kazuhiko Yoshida , Yukio Yano
发明人： Kazunori Oyabe , Tatsuhiko Fujihira , Kazuhiko Yoshida , Yukio Yano
IPC分类号： H03K17/08 , H03K17/00 , H03K17/082 , H03K17/695 , H03K3/00
CPC分类号： H03K17/0822 , H03K17/0828 , H03K2217/0036
摘要： A gate drive circuit device for a voltage-driven semiconductor element reduces the time to dissipate inductively stored electromagnetic energy and reduces current consumption by using cyclically charged capacitative storage to produce a control signal that is about twice the supply voltage. This permits full-ON dissipation of the stored energy after the circuit cuts off power to the inductive element. In one embodiment, the dissipation is chiefly in a voltage-regulator diode connected to limit the voltage appearing across a transistor. In another embodiment, a voltage regulator diode permits a transistor to operate in the full-on condition, while limiting the voltage across it to a value below its withstand voltage, whereby a maximum power dissipation current flows in the transistor. In a further embodiment a gate drive signal generator eliminates a voltage regulator diode from the conventional gate drive circuit device. Instead, this embodiment substitutes switching devices both on the power supply side and the reference potential (ground) side. Both switching devices include a switch and an operating section that controls switching operation. The two operating sections receive an externally generated command signal for timing the ON/OFF operation of the switches. The control technique permits both the switching and operating sections to be fabricated integrally as an integrated circuit.
摘要翻译：用于电压驱动的半导体元件的栅极驱动电路器件通过使用循环充电的电容存储来减少耗散感应存储的电磁能量并减少电流消耗的时间，以产生大约是电源电压的两倍的控制信号。这在电路断开电感元件的电源之后，允许存储能量的全功耗。在一个实施例中，耗散主要在连接的电压调节器二极管中以限制出现在晶体管两端的电压。在另一个实施例中，电压调节器二极管允许晶体管在全开状态下工作，同时将其两端的电压限制在低于其耐受电压的值，由此在晶体管中流过最大功耗电流。在另一实施例中，栅极驱动信号发生器从传统的栅极驱动电路器件中消除了稳压二极管。相反，该实施例将电源侧和参考电位（接地）侧的开关器件替代。两个开关装置包括开关和控制开关操作的操作部分。两个操作部分接收外部产生的命令信号以定时开关的ON / OFF操作。控制技术允许开关和操作部分作为集成电路整体制造。

2. 发明授权

US5621601A Over-current protection apparatus for transistor 失效
标题翻译：晶体管过电流保护装置
公开(公告)号：US5621601A
公开(公告)日：1997-04-15
申请号：US314320
申请日：1994-09-28
申请人： Tatsuhiko Fujihira , Shin Kiuchi , Kazuhiko Yoshida , Yukio Yano , Kazunori Oyabe , Shoichi Furuhata , Tetsuhiro Morimoto
发明人： Tatsuhiko Fujihira , Shin Kiuchi , Kazuhiko Yoshida , Yukio Yano , Kazunori Oyabe , Shoichi Furuhata , Tetsuhiro Morimoto
IPC分类号： H01L29/78 , G05F1/56 , H01L27/02 , H01L27/04 , H02H7/12 , H02M1/00 , H03K17/082 , H02H3/00
CPC分类号： H03K17/0822 , H01L27/0248 , H03F1/52 , H03K17/0828
摘要： The disclosed invention is designed to prevent the oscillation which often occurs in an over-current protection apparatus for an insulated gate controlled transistor. The apparatus improves the response in current detection, to prevent oscillation, and improves protection speed against over-current. This is accomplished by separating the gates of the main transistor and the current detector transistor; by setting a shorter time constant for the gate circuit of the current detector transistor than that of the gate circuit of the main transistor; by feeding the detection signal obtained from the current detecting means which detects the current i of the current detector transistor proportional to the current I flowing through the main transistor, to the control means; and by controlling the gate potentials of both transistors to protect the main transistor from the over-current by feeding the comparison output Sd from the comparator circuit, which compares the voltage of the signal Vd with the reference voltage Vr, to the control circuit.
摘要翻译：所公开的发明被设计为防止在绝缘栅极控制晶体管的过电流保护装置中经常发生的振荡。该装置提高了电流检测中的响应，防止振荡，提高了防过电流的保护速度。这通过分离主晶体管和电流检测器晶体管的栅极来实现; 通过为电流检测器晶体管的栅极电路设置比主晶体管的栅极电路的时间常数更短的时间常数; 通过将检测到与流过主晶体管的电流I成比例的电流检测器晶体管的电流i的电流检测装置获得的检测信号馈送到控制装置; 并且通过控制两个晶体管的栅极电位，通过将比较电路的比较输出Sd与信号Vd与参考电压Vr进行比较来控制主晶体管的过电流来保护主晶体管。

3. 发明授权

US5587655A Constant current circuit 失效
标题翻译：恒流电路
公开(公告)号：US5587655A
公开(公告)日：1996-12-24
申请号：US514208
申请日：1995-08-11
申请人： Kazunori Oyabe , Kazuhiko Yoshida , Tatsuhiko Fujihira
发明人： Kazunori Oyabe , Kazuhiko Yoshida , Tatsuhiko Fujihira
IPC分类号： G05F3/24 , G05F3/26 , G05F3/04 , G05F3/16
CPC分类号： G05F3/262 , Y10S323/907
摘要： A constant current circuit of the invention supplies a constant current to a load. The constant current circuit is formed of a current source device for providing an input current having a predetermined value with temperature dependence, a voltage divider device connected to the current source device, and an output transistor device. A reference transistor device or an adjusting transistor device is attached to the current source device. In case the reference transistor device is used, the voltage divider device divides a reference voltage of the reference transistor device to thereby generate a control voltage. In case the adjusting transistor device is used, an adjusting voltage from the voltage divider device is supplied to the adjusting transistor device to generate a control voltage. The output transistor device is connected to the load for controlling an output current supplied to the load in response to the control voltage. Temperature dependence of the output current is adjusted by setting voltage dividing ratio of the voltage divider device.
摘要翻译：本发明的恒流电路向负载提供恒定电流。恒流电路由电流源装置形成，用于提供具有温度依赖性的预定值的输入电流，连接到电流源装置的分压器件和输出晶体管器件。参考晶体管器件或调节晶体管器件附接到电流源器件。在使用参考晶体管器件的情况下，分压器器件分割参考晶体管器件的参考电压，从而产生控制电压。在使用调节晶体管器件的情况下，来自分压器件的调节电压被提供给调节晶体管器件以产生控制电压。输出晶体管器件连接到负载，用于响应于控制电压控制提供给负载的输出电流。通过设定分压器的分压比来调节输出电流的温度依赖性。

4. 发明授权

US06124628A High voltage integrated circuit, high voltage junction terminating structure, and high voltage MIS transistor 失效
标题翻译：高压集成电路，高压结端接结构和高电压MIS晶体管
公开(公告)号：US06124628A
公开(公告)日：2000-09-26
申请号：US631017
申请日：1996-04-12
申请人： Tatsuhiko Fujihira , Yukio Yano , Shigeyuki Obinata , Naoki Kumagai
发明人： Tatsuhiko Fujihira , Yukio Yano , Shigeyuki Obinata , Naoki Kumagai
IPC分类号： H01L27/06 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/40 , H01L29/78 , H01L33/00
CPC分类号： H01L29/404 , H01L27/0623 , H01L27/0922 , H01L29/7809 , H01L29/7811 , H01L29/7835 , H01L29/0615 , H01L29/405 , H01L2924/14
摘要： A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a selected area of a surface of the second region; first source region and first drain region of the first conductivity type formed in the second region, apart from the third region; a first gate electrode formed on a surface of the second region between the first source region and first drain region, through an insulating film; second source region and second drain region of second conductivity type formed in a surface of the third region; and a second gate electrode formed on a surface of the third region between the second source region and the second drain region, through an insulating film.
摘要翻译：提供了一种高压集成电路，其包括第一导电类型的第一区域; 形成在所述第一区域的第一主表面中的第二导电类型的第二区域; 形成在所述第二区域的表面的选定区域中的第一导电类型的第三区域; 形成在第二区域中的第一导电类型的第一源极区域和第一漏极区域; 通过绝缘膜形成在第一区域和第一漏极区域之间的第二区域的表面上的第一栅电极; 形成在第三区域的表面中的第二导电类型的第二源极区域和第二漏极区域; 以及通过绝缘膜形成在第二源极区域和第二漏极区域之间的第三区域的表面上的第二栅极电极。

5. 发明授权

US06323539B1 High voltage integrated circuit, high voltage junction terminating structure, and high voltage MIS transistor 有权
标题翻译：高压集成电路，高压结端接结构和高电压MIS晶体管
公开(公告)号：US06323539B1
公开(公告)日：2001-11-27
申请号：US09639738
申请日：2000-08-16
申请人： Tatsuhiko Fujihira , Yukio Yano , Shigeyuki Obinata , Naoki Kumagai
发明人： Tatsuhiko Fujihira , Yukio Yano , Shigeyuki Obinata , Naoki Kumagai
IPC分类号： H01L2978
CPC分类号： H01L27/0623 , H01L21/823481 , H01L27/088 , H01L27/092 , H01L27/0922 , H01L27/0928 , H01L29/0615 , H01L29/1083 , H01L29/402 , H01L29/404 , H01L29/405 , H01L29/7809 , H01L29/7811 , H01L29/7835 , H01L29/8611 , H01L2924/13055 , H01L2924/13091 , H01L2924/14
摘要： A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a selected area of a surface of the second region; first source region and first drain region of the first conductivity type formed in the second region, apart from the third region; a first gate electrode formed on a surface of the second region between the first source region and first drain region, through an insulating film; second source region and second drain region of second conductivity type formed in a surface of the third region; and a second gate electrode formed on a surface of the third region between the second source region and the second drain region, through an insulating film.
摘要翻译：提供了一种高压集成电路，其包括第一导电类型的第一区域; 形成在所述第一区域的第一主表面中的第二导电类型的第二区域; 形成在所述第二区域的表面的选定区域中的第一导电类型的第三区域; 第一导电类型的第一源极区域和第一漏极区域形成在第二区域中; 通过绝缘膜形成在第一区域和第一漏极区域之间的第二区域的表面上的第一栅电极; 形成在第三区域的表面中的第二导电类型的第二源极区域和第二漏极区域; 以及通过绝缘膜形成在第二源极区域和第二漏极区域之间的第三区域的表面上的第二栅极电极。

6. 发明授权

US07476935B2 High power semiconductor device having a schottky barrier diode 有权
标题翻译：具有肖特基势垒二极管的大功率半导体器件
公开(公告)号：US07476935B2
公开(公告)日：2009-01-13
申请号：US11054856
申请日：2005-02-10
申请人： Naoki Kumagai , Yuuichi Harada , Shinichi Jimbo , Yoshihiro Ikura , Tatsuhiko Fujihira , Kazuhiko Yoshida
发明人： Naoki Kumagai , Yuuichi Harada , Shinichi Jimbo , Yoshihiro Ikura , Tatsuhiko Fujihira , Kazuhiko Yoshida
IPC分类号： H01L29/78
CPC分类号： H01L27/0255 , H01L27/0727 , H01L29/1087 , H01L29/47 , H01L29/7835
摘要： A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
摘要翻译：半导体器件被配置为当在单个芯片上形成桥接电路的MOSFET时，通过由寄生晶体管产生的寄生效应来防止元件的损坏和/或错误操作。通过在横向MOSFET的源极区，漏极区和p阱区的n阱区域中设置阳极电极形成肖特基结。构成多数载波器件的肖特基势垒二极管与能够正向偏置的PN结并联连接，使得PN结不被正向偏置，从而不产生少数载流子，从而抑制寄生效应。

7. 发明申请

US20060022265A1 Semiconductor device having a lateral MOSFET and combined IC using the same 有权
标题翻译：具有横向MOSFET的半导体器件和使用其的组合IC
公开(公告)号：US20060022265A1
公开(公告)日：2006-02-02
申请号：US11235415
申请日：2005-09-26
申请人： Kazuhiko Yoshida , Takeshi Ichimura , Tatsuhiko Fujihira , Naoki Kumagai
发明人： Kazuhiko Yoshida , Takeshi Ichimura , Tatsuhiko Fujihira , Naoki Kumagai
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L27/0251 , H01L29/7817 , H01L29/7821 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.
摘要翻译：半导体器件在集成智能开关器件，双积分型信号输入和转换IC以及组合电源IC中使用的横向MOSFET的窄芯片区域内实现了高静电放电耐受能力和高耐冲击能力。半导体器件包括其中基极电连接到发射极和集电极的垂直双极晶体管，以及包括连接到表面电极的漏电极的横向MOSFET。当施加高静电放电电压或高浪涌电压时，垂直双极晶体管吸收静电放电或浪涌能量，并将静电放电电压或浪涌电压限制为低于横向MOSFET的击穿电压。

8. 发明授权

US06870223B2 High power semiconductor device having a Schottky barrier diode 有权
标题翻译：具有肖特基势垒二极管的大功率半导体器件
公开(公告)号：US06870223B2
公开(公告)日：2005-03-22
申请号：US10301489
申请日：2002-11-21
申请人： Naoki Kumagai , Yuuichi Harada , Shinichi Jimbo , Yoshihiro Ikura , Tatsuhiko Fujihira , Kazuhiko Yoshida
发明人： Naoki Kumagai , Yuuichi Harada , Shinichi Jimbo , Yoshihiro Ikura , Tatsuhiko Fujihira , Kazuhiko Yoshida
IPC分类号： H01L29/872 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/07 , H01L27/088 , H01L29/10 , H01L29/47 , H01L29/78
CPC分类号： H01L27/0255 , H01L27/0727 , H01L29/1087 , H01L29/47 , H01L29/7835
摘要： A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
摘要翻译：半导体器件被配置为当在单个芯片上形成桥接电路的MOSFET时，通过由寄生晶体管产生的寄生效应来防止元件的损坏和/或错误操作。通过在横向MOSFET的源极区，漏极区和p阱区的n阱区域中设置阳极电极形成肖特基结。构成多数载波器件的肖特基势垒二极管与能够正向偏置的PN结并联连接，使得PN结不被正向偏置，从而不产生少数载流子，从而抑制寄生效应。

9. 发明授权

US07247923B2 Semiconductor device having a lateral MOSFET and combined IC using the same 有权
标题翻译：具有横向MOSFET的半导体器件和使用其的组合IC
公开(公告)号：US07247923B2
公开(公告)日：2007-07-24
申请号：US11235415
申请日：2005-09-26
申请人： Kazuhiko Yoshida , Takeshi Ichimura , Tatsuhiko Fujihira , Naoki Kumagai
发明人： Kazuhiko Yoshida , Takeshi Ichimura , Tatsuhiko Fujihira , Naoki Kumagai
IPC分类号： H01L29/00
CPC分类号： H01L29/7816 , H01L27/0251 , H01L29/7817 , H01L29/7821 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.
摘要翻译：半导体器件在集成智能开关器件，双积分型信号输入和转换IC以及组合电源IC中使用的横向MOSFET的窄芯片区域内实现了高静电放电耐受能力和高耐冲击能力。半导体器件包括其中基极电连接到发射极和集电极的垂直双极晶体管，以及包括连接到表面电极的漏电极的横向MOSFET。当施加高静电放电电压或高浪涌电压时，垂直双极晶体管吸收静电放电或浪涌能量，并将静电放电电压或浪涌电压限制为低于横向MOSFET的击穿电压。

10. 发明授权

US06229180B1 MOS type semiconductor apparatus 有权
公开(公告)号：US06229180B1
公开(公告)日：2001-05-08
申请号：US09238855
申请日：1999-01-27
申请人： Kazuhiko Yoshida , Tatsuhiko Fujihira , Motoi Kudoh , Shoichi Furuhata , Shigeyuki Takeuchi
发明人： Kazuhiko Yoshida , Tatsuhiko Fujihira , Motoi Kudoh , Shoichi Furuhata , Shigeyuki Takeuchi
IPC分类号： H01L2362
CPC分类号： H01L29/7395 , H01L25/071 , H01L27/0255 , H01L27/0635 , H01L29/1095 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.

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