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1. 发明授权

US07531402B2 Method of manufacturing semiconductor device with offset sidewall structure 有权
公开(公告)号：US07531402B2
公开(公告)日：2009-05-12
申请号：US11742990
申请日：2007-05-01
申请人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
发明人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
IPC分类号： H01L21/8238
CPC分类号： H01L29/42368 , H01L21/02164 , H01L21/0217 , H01L21/265 , H01L21/28017 , H01L21/28158 , H01L21/823814 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

2. 发明授权

US07563663B2 Method of manufacturing semiconductor device with offset sidewall structure 有权
标题翻译：具有偏移侧壁结构的半导体器件的制造方法
公开(公告)号：US07563663B2
公开(公告)日：2009-07-21
申请号：US11743021
申请日：2007-05-01
申请人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
发明人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/42368 , H01L21/02164 , H01L21/0217 , H01L21/265 , H01L21/28017 , H01L21/28158 , H01L21/823814 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
摘要翻译：提供一种制造具有NMOS和PMOS晶体管的半导体器件的方法。半导体器件可以减小短沟道效应，可以减少栅极漏极电流泄漏，并且可以减少由于栅极重叠引起的寄生电容，从而抑制电路的操作速度的降低。在低压NMOS区域（LNR）中的硅衬底（1）的表面中离子注入诸如砷的N型杂质，从而形成延伸层（61）。然后，形成氧化硅膜（OX2）以覆盖硅衬底（1）的整个表面。栅电极（51-54）侧面上的氧化硅膜（OX2）用作偏移侧壁。然后，在低压PMOS区域（LPR）中，在硅衬底（1）的表面中将硼离子注入到相对较低的浓度上，从而形成稍后为延伸层（62）的P型杂质层（621）。

3. 发明授权

US07220637B2 Method of manufacturing semiconductor device with offset sidewall structure 有权
标题翻译：具有偏移侧壁结构的半导体器件的制造方法
公开(公告)号：US07220637B2
公开(公告)日：2007-05-22
申请号：US10212252
申请日：2002-08-06
申请人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
发明人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
IPC分类号： H01L21/8239
CPC分类号： H01L29/42368 , H01L21/02164 , H01L21/0217 , H01L21/265 , H01L21/28017 , H01L21/28158 , H01L21/823814 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51–54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
摘要翻译：提供一种制造具有NMOS和PMOS晶体管的半导体器件的方法。半导体器件可以减小短沟道效应，可以减少栅极漏极电流泄漏，并且可以减少由于栅极重叠引起的寄生电容，从而抑制电路的操作速度的降低。在低电压NMOS区域（LNR）中的硅衬底（1）的表面中，将诸如砷的N型杂质离子注入到相对较低的浓度，从而形成扩展层（61）。然后，形成氧化硅膜（OX 2）以覆盖硅衬底（1）的整个表面。在栅电极（51-54）的侧面上的氧化硅膜（OX 2）用作偏移侧壁。然后，在低压PMOS区域（LPR）中，在硅衬底（1）的表面中将硼离子注入到相对较低的浓度上，从而形成稍后为延伸层（62）的P型杂质层（621）。

4. 发明授权

US08415213B2 Method of manufacturing semiconductor device with offset sidewall structure 有权
公开(公告)号：US08415213B2
公开(公告)日：2013-04-09
申请号：US13185624
申请日：2011-07-19
申请人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
发明人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
IPC分类号： H01L21/8238
CPC分类号： H01L29/42368 , H01L21/02164 , H01L21/0217 , H01L21/265 , H01L21/28017 , H01L21/28158 , H01L21/823814 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

5. 发明授权

US07998802B2 Method of manufacturing semiconductor device with offset sidewall structure 有权
标题翻译：具有偏移侧壁结构的半导体器件的制造方法
公开(公告)号：US07998802B2
公开(公告)日：2011-08-16
申请号：US12484618
申请日：2009-06-15
申请人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
发明人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/42368 , H01L21/02164 , H01L21/0217 , H01L21/265 , H01L21/28017 , H01L21/28158 , H01L21/823814 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
摘要翻译：提供一种制造具有NMOS和PMOS晶体管的半导体器件的方法。半导体器件可以减小短沟道效应，可以减少栅极漏极电流泄漏，并且可以减少由于栅极重叠引起的寄生电容，从而抑制电路的操作速度的降低。在低压NMOS区域（LNR）中的硅衬底（1）的表面中离子注入诸如砷的N型杂质，从而形成延伸层（61）。然后，形成氧化硅膜（OX2）以覆盖硅衬底（1）的整个表面。栅电极（51-54）侧面上的氧化硅膜（OX2）用作偏移侧壁。然后，在低压PMOS区域（LPR）中，在硅衬底（1）的表面中将硼离子注入到相对低的浓度，从而形成稍后为扩展层（62）的P型杂质层（621）。

6. 发明申请

US20090253235A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE 有权
标题翻译：制造具有偏心结构的半导体器件的方法
公开(公告)号：US20090253235A1
公开(公告)日：2009-10-08
申请号：US12484618
申请日：2009-06-15
申请人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
发明人： Kazunobu Ota , Hirokazu Sayama , Hidekazu Oda
IPC分类号： H01L21/8238
CPC分类号： H01L29/42368 , H01L21/02164 , H01L21/0217 , H01L21/265 , H01L21/28017 , H01L21/28158 , H01L21/823814 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
摘要翻译：提供一种制造具有NMOS和PMOS晶体管的半导体器件的方法。半导体器件可以减小短沟道效应，可以减少栅极漏极电流泄漏，并且可以减少由于栅极重叠引起的寄生电容，从而抑制电路的操作速度的降低。在低压NMOS区域（LNR）中的硅衬底（1）的表面中离子注入诸如砷的N型杂质，从而形成延伸层（61）。然后，形成氧化硅膜（OX2）以覆盖硅衬底（1）的整个表面。栅电极（51-54）侧面上的氧化硅膜（OX2）用作偏移侧壁。然后，在低压PMOS区域（LPR）中，在硅衬底（1）的表面中将硼离子注入到相对低的浓度，从而形成稍后为扩展层（62）的P型杂质层（621）。

7. 发明申请

US20060273394A1 Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060273394A1
公开(公告)日：2006-12-07
申请号：US11503156
申请日：2006-08-14
申请人： Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
发明人： Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
IPC分类号： H01L29/78 , H01L23/52
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/12 , H01L27/1203 , H01L29/4238 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/78615 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).
摘要翻译：提供一种半导体器件，其通过降低寄生双极晶体管的增益来实现故障的减小和工作特性变化，及其制造方法。在硅层（3）的上表面上部分地形成氧化硅膜（6）。多晶硅的栅电极（7）部分地形成在氧化硅膜（6）上。栅电极（7）下方的氧化硅膜（6）的一部分用作栅极绝缘膜。在栅极（7）的每个侧表面上形成氮化硅膜（9），其间具有氧化硅膜（8）。氧化硅膜（8）和氮化硅膜（9）形成在氧化硅膜（6）上。氧化硅膜（8）在栅极长度方向上的宽度（W1）大于氧化硅膜（6）的厚度（T 1）。

8. 发明授权

US06806537B2 Semiconductor device having offset insulation film formed on insulation film, and method of manufacturing the same 有权
标题翻译：具有在绝缘膜上形成的偏移绝缘膜的半导体器件及其制造方法
公开(公告)号：US06806537B2
公开(公告)日：2004-10-19
申请号：US10192657
申请日：2002-07-11
申请人： Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
发明人： Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/12 , H01L27/1203 , H01L29/4238 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/78615 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).
摘要翻译：提供一种半导体器件，其通过降低寄生双极晶体管的增益来实现故障的减小和工作特性变化，及其制造方法。在硅层（3）的上表面上部分地形成氧化硅膜（6）。多晶硅的栅电极（7）部分地形成在氧化硅膜（6）上。栅电极（7）下方的氧化硅膜（6）的一部分用作栅极绝缘膜。在栅极（7）的每个侧表面上形成氮化硅膜（9），其间具有氧化硅膜（8）。氧化硅膜（8）和氮化硅膜（9）形成在氧化硅膜（6）上。氧化硅膜（8）在栅极长度方向上的宽度（W1）大于氧化硅膜（6）的厚度（T1）。

9. 发明授权

US07109553B2 Semiconductor device and method of manufacturing same 有权
公开(公告)号：US07109553B2
公开(公告)日：2006-09-19
申请号：US10866701
申请日：2004-06-15
申请人： Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
发明人： Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/12 , H01L27/1203 , H01L29/4238 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/78615 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).

10. 发明授权

US07170109B2 Heterojunction semiconductor device with element isolation structure 失效
标题翻译：具有元件隔离结构的异质结半导体器件
公开(公告)号：US07170109B2
公开(公告)日：2007-01-30
申请号：US10864457
申请日：2004-06-10
申请人： Kohei Sugihara , Kazunobu Ota , Hidekazu Oda , Takahashi Hayashi
发明人： Kohei Sugihara , Kazunobu Ota , Hidekazu Oda , Takahashi Hayashi
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336 , H01L23/48
CPC分类号： H01L21/823481 , H01L21/76224 , H01L2924/0002 , H01L2924/00
摘要： A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench. Since the semiconductor film is interposed between the compound semiconductor film which is exposed by the trench and the first insulating film, there is no possibility that the compound semiconductor layer is directly thermally oxidized even if the semiconductor film is thermally oxidized to form the first insulating film.
摘要翻译：提供了能够提高半导体器件的元件隔离特性的技术。在其中硅层，化合物半导体层和半导体层依次层叠的半导体衬底中提供元件隔离结构。元件隔离结构由沟槽，半导体膜以及第一和第二绝缘膜构成。沟槽延伸穿过半导体层并延伸到化合物半导体层的内部。半导体膜设置在沟槽的表面上，第一绝缘膜设置在半导体膜上。第二绝缘膜设置在第一绝缘膜上并填充沟槽。由于半导体膜介于通过沟槽暴露的化合物半导体膜和第一绝缘膜之间，即使半导体膜被热氧化以形成第一绝缘膜，化合物半导体层也不可能直接热氧化。

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