专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080104365A1 CONFIGURABLE PROCESSOR DESIGN APPARATUS AND DESIGN METHOD, LIBRARY OPTIMIZATION METHOD, PROCESSOR, AND FABRICATION METHOD FOR SEMICONDUCTOR DEVICE INCLUDING PROCESSOR 有权
标题翻译：可配置处理器设计和设计方法，图书馆优化方法，包括处理器的半导体器件的处理器和制造方法
公开(公告)号：US20080104365A1
公开(公告)日：2008-05-01
申请号：US11957781
申请日：2007-12-17
申请人： Kazuhyoshi Kohno , Atsushi Mizuno , Atsushi Masuda , Ryuichiro Ohyama , Yutaka Ota
发明人： Kazuhyoshi Kohno , Atsushi Mizuno , Atsushi Masuda , Ryuichiro Ohyama , Yutaka Ota
IPC分类号： G06F15/00
CPC分类号： G06F17/5045 , G06F8/4434 , G06F17/5022
摘要： A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.
摘要翻译：一种用于设计用于应用的可重配置的处理器的设计装置，包括：分析单元，分析由处理器执行的程序的内容; 硬件扩展单元，其根据分析单元的分析结果搜索程序的一部分，允许硬件扩展，并产生搜索到的部分的硬件扩展信息; 扩展指令定义单元，其根据分析单元的分析结果搜索程序中允许使用扩展指令的部分，并生成所搜索的部分的扩展指令的定义; 以及性能估计单元，其使用由所述硬件扩展单元生成的硬件扩展信息和由所述扩展指令定义单元生成的扩展指令的定义中的至少一个来估计所述处理器的性能是否满足目标性能。

2. 发明授权

US07707386B2 Program segment searching for extension instruction determination to design a processor that meets performance goal 有权
标题翻译：程序段搜索扩展指令确定以设计满足性能目标的处理器
公开(公告)号：US07707386B2
公开(公告)日：2010-04-27
申请号：US11957781
申请日：2007-12-17
申请人： Kazuyoshi Kohno , Atsushi Mizuno , Atsushi Masuda , Ryuichiro Ohyama , Yutaka Ota
发明人： Kazuyoshi Kohno , Atsushi Mizuno , Atsushi Masuda , Ryuichiro Ohyama , Yutaka Ota
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F8/4434 , G06F17/5022
摘要： A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.
摘要翻译：一种用于设计用于应用的可重配置的处理器的设计装置，包括：分析单元，分析由处理器执行的程序的内容; 硬件扩展单元，其根据分析单元的分析结果搜索程序的一部分，允许硬件扩展，并产生搜索到的部分的硬件扩展信息; 扩展指令定义单元，其根据分析单元的分析结果搜索程序中允许使用扩展指令的部分，并生成所搜索的部分的扩展指令的定义; 以及性能估计单元，其使用由所述硬件扩展单元生成的硬件扩展信息和由所述扩展指令定义单元生成的扩展指令的定义中的至少一个来估计所述处理器的性能是否满足目标性能。

3. 发明授权

US07337301B2 Designing configurable processor with hardware extension for instruction extension to replace searched slow block of instructions 失效
标题翻译：设计具有硬件扩展的可配置处理器，用于指令扩展，以替代搜索慢的指令块
公开(公告)号：US07337301B2
公开(公告)日：2008-02-26
申请号：US11044085
申请日：2005-01-28
申请人： Kazuyoshi Kohno , Atsushi Mizuno , Atsushi Masuda , Ryuichiro Ohyama , Yutaka Ota
发明人： Kazuyoshi Kohno , Atsushi Mizuno , Atsushi Masuda , Ryuichiro Ohyama , Yutaka Ota
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F8/4434 , G06F17/5022
摘要： A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.
摘要翻译：一种用于设计用于应用的可配置处理器的设计装置，包括：分析单元，分析由处理器执行的程序的内容; 硬件扩展单元，其根据分析单元的分析结果搜索程序的一部分，允许硬件扩展，并产生搜索到的部分的硬件扩展信息; 扩展指令定义单元，其根据分析单元的分析结果搜索程序中允许使用扩展指令的部分，并生成所搜索的部分的扩展指令的定义; 以及性能估计单元，其使用由所述硬件扩展单元生成的硬件扩展信息和由所述扩展指令定义单元生成的所述扩展指令的定义中的至少一个来估计所述处理器的性能是否满足目标性能。

4. 发明申请

US20050193184A1 Configurable processor design apparatus and design method, library optimization method, processor, and fabrication method for semiconductor device including processor 失效
标题翻译：包括处理器的半导体器件的可配置处理器设计和设计方法，库优化方法，处理器和制造方法
公开(公告)号：US20050193184A1
公开(公告)日：2005-09-01
申请号：US11044085
申请日：2005-01-28
申请人： Kazuyoshi Kohno , Atsushi Mizuno , Atsushi Masuda , Ryuichiro Ohyama , Yutaka Ota
发明人： Kazuyoshi Kohno , Atsushi Mizuno , Atsushi Masuda , Ryuichiro Ohyama , Yutaka Ota
IPC分类号： G06F17/50 , G06F9/45 , G06F15/00
CPC分类号： G06F17/5045 , G06F8/4434 , G06F17/5022
摘要： A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.
摘要翻译：一种用于设计用于应用的可配置处理器的设计装置，包括：分析单元，分析由处理器执行的程序的内容; 硬件扩展单元，其根据分析单元的分析结果搜索程序的一部分，允许硬件扩展，并产生搜索到的部分的硬件扩展信息; 扩展指令定义单元，其根据分析单元的分析结果搜索程序中允许使用扩展指令的部分，并生成所搜索的部分的扩展指令的定义; 以及性能估计单元，其使用由所述硬件扩展单元生成的硬件扩展信息和由所述扩展指令定义单元生成的所述扩展指令的定义中的至少一个来估计所述处理器的性能是否满足目标性能。

5. 发明授权

US07340692B2 System LSI development apparatus and the method thereof for developing a system optimal to an application 有权
标题翻译：系统LSI开发装置及其开发适用于应用的系统的方法
公开(公告)号：US07340692B2
公开(公告)日：2008-03-04
申请号：US10621449
申请日：2003-07-18
申请人： Nobuo Matsui , Atsushi Mizuno , Ryuichiro Ohyama , Megumi Tangoda , Katsuya Uchida
发明人： Nobuo Matsui , Atsushi Mizuno , Ryuichiro Ohyama , Megumi Tangoda , Katsuya Uchida
IPC分类号： G06F17/50 , G06F13/10
CPC分类号： G06F17/5022 , G06F17/5045
摘要： In this disclosure, based on change item definition information concerning system LSI development and design, software used for development and design of a system LSI that contains a processor having optional instructions defined therein is operated, and system LSI hardware description, verification environment and a development and design tools are generated, thus making it possible to develop a system LSI optimal to an application within a short period.
摘要翻译：在本公开中，基于关于系统LSI开发和设计的改变项目定义信息，操作用于开发和设计包含其中定义的可选指令的处理器的系统LSI的软件，并且系统LSI硬件描述，验证环境和开发并产生设计工具，从而可以在短时间内为应用开发最佳的系统LSI。

6. 发明申请

US20050076314A1 System LSI development apparatus and the method thereof for developing a system optimal to an application 有权
标题翻译：系统LSI开发装置及其开发适用于应用的系统的方法
公开(公告)号：US20050076314A1
公开(公告)日：2005-04-07
申请号：US10621449
申请日：2003-07-18
申请人： Nobuo Matsui , Atsushi Mizuno , Ryuichiro Ohyama , Megumi Tangoda , Katsuya Uchida
发明人： Nobuo Matsui , Atsushi Mizuno , Ryuichiro Ohyama , Megumi Tangoda , Katsuya Uchida
IPC分类号： G06F11/22 , G06F11/26 , G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： In this disclosure, based on change item definition information concerning system LSI development and design, software used for development and design of a system LSI that contains a processor having optional instructions defined therein is operated, and system LSI hardware description, verification environment and a development and design tools are generated, thus making it possible to develop a system LSI optimal to an application within a short period.
摘要翻译：在本公开中，基于关于系统LSI开发和设计的改变项目定义信息，操作用于开发和设计包含其中定义的可选指令的处理器的系统LSI的软件，并且系统LSI硬件描述，验证环境和开发并产生设计工具，从而可以在短时间内为应用开发最佳的系统LSI。

7. 发明授权

US06634017B2 System LSI development apparatus and the method thereof for developing a system optimal to an application 有权
标题翻译：系统LSI开发装置及其开发适用于应用的系统的方法
公开(公告)号：US06634017B2
公开(公告)日：2003-10-14
申请号：US09865289
申请日：2001-05-29
申请人： Nobuo Matsui , Atsushi Mizuno , Ryuichiro Ohyama , Megumi Tangoda , Katsuya Uchida
发明人： Nobuo Matsui , Atsushi Mizuno , Ryuichiro Ohyama , Megumi Tangoda , Katsuya Uchida
IPC分类号： G06F9455
CPC分类号： G06F17/5022 , G06F17/5045
摘要： In this disclosure, based on change item definition information concerning system LSI development and design, software used for development and design of a system LSI that contains a processor having optional instructions defined therein is operated, and system LSI hardware description, verification environment and a development and design tools are generated, thus making it possible to develop a system LSI optimal to an application within a short period.
摘要翻译：在本公开中，基于关于系统LSI开发和设计的改变项目定义信息，操作用于开发和设计包含其中定义的可选指令的处理器的系统LSI的软件，并且系统LSI硬件描述，验证环境和开发并产生设计工具，从而可以在短时间内为应用开发最佳的系统LSI。

8. 发明申请

US20100299541A1 MULTI-CORE PROCESSOR SYSTEM 有权
标题翻译：多核处理器系统
公开(公告)号：US20100299541A1
公开(公告)日：2010-11-25
申请号：US12610472
申请日：2009-11-02
申请人： Yuji Ishikawa , Toshiki Kizu , Ryuichiro Ohyama
发明人： Yuji Ishikawa , Toshiki Kizu , Ryuichiro Ohyama
IPC分类号： G06F1/00
CPC分类号： G06F9/4893 , G06F1/3228 , G06F9/5027 , G06F9/5094 , G06F2209/5018 , Y02D10/22 , Y02D10/24
摘要： A multi-core processor system includes: a plurality of processor cores; a power supply unit that stops supplying or supplies power to each of the processor cores individually; and a thread queue that stores threads that the multi-core processor system causes the processor cores to execute. Each of the processor cores includes: a power-supply stopping unit that causes the power supply unit to stop power supply to an own processor core when a number of threads stored in the thread queue is equal to or smaller than a first threshold; and a power-supply resuming unit that causes the power supply unit to resume power supply to the other stopped processor cores when the number of threads stored in the thread queue exceeds a second value equal to or lager than the first threshold.
摘要翻译：多核处理器系统包括：多个处理器核; 电源单元，其分别停止向每个处理器核心供电或供电; 以及存储多核处理器系统使处理器核心执行的线程的线程队列。每个处理器核心包括：电源停止单元，当存储在线程队列中的线程数等于或小于第一阈值时，使电源单元停止向自己的处理器核心供电; 以及电源恢复单元，当存储在所述线程队列中的线程数超过等于或大于所述第一阈值的第二值时，所述电源恢复单元使得所述电源单元恢复向所述其他停止的处理器核心的电力供应。

9. 发明授权

US07168060B2 Method of generating development environment for developing system LSI and medium which stores program therefor using VLIW designating description 失效
标题翻译：用于开发系统LSI的开发环境的生成方法和使用VLIW指定描述存储其程序的介质
公开(公告)号：US07168060B2
公开(公告)日：2007-01-23
申请号：US10197891
申请日：2002-07-19
申请人： Nobu Matsumoto , Ryuichiro Ohyama , Katsuya Uchida
发明人： Nobu Matsumoto , Ryuichiro Ohyama , Katsuya Uchida
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A system LSI development environment generating method includes a compiler customizing section which generates a compiler from a configuration designation file, an assembler customizing section which generates an assembler, and a simulator generating section which generates a simulator. The configuration designation file contains a designation of hardware which executes instructions.
摘要翻译：系统LSI开发环境生成方法包括从配置指定文件生成编译器的编译器定制部分，生成汇编器的汇编器定制部分，以及生成模拟器的模拟器生成部。配置指定文件包含执行指令的硬件的指定。

10. 发明授权

US08214679B2 Multi-core processor system with thread queue based power management 有权
标题翻译：具有线程队列功能管理的多核处理器系统
公开(公告)号：US08214679B2
公开(公告)日：2012-07-03
申请号：US12610472
申请日：2009-11-02
申请人： Yuji Ishikawa , Toshiki Kizu , Ryuichiro Ohyama
发明人： Yuji Ishikawa , Toshiki Kizu , Ryuichiro Ohyama
IPC分类号： G06F1/32
CPC分类号： G06F9/4893 , G06F1/3228 , G06F9/5027 , G06F9/5094 , G06F2209/5018 , Y02D10/22 , Y02D10/24
摘要： A multi-core processor system includes: a plurality of processor cores; a power supply unit that stops supplying or supplies power to each of the processor cores individually; and a thread queue that stores threads that the multi-core processor system causes the processor cores to execute. Each of the processor cores includes: a power-supply stopping unit that causes the power supply unit to stop power supply to an own processor core when a number of threads stored in the thread queue is equal to or smaller than a first threshold; and a power-supply resuming unit that causes the power supply unit to resume power supply to the other stopped processor cores when the number of threads stored in the thread queue exceeds a second value equal to or lager than the first threshold.
摘要翻译：多核处理器系统包括：多个处理器核; 电源单元，其分别停止向每个处理器核心供电或供电; 以及存储多核处理器系统使处理器核心执行的线程的线程队列。每个处理器核心包括：电源停止单元，当存储在线程队列中的线程数等于或小于第一阈值时，使电源单元停止向自己的处理器核心供电; 以及电源恢复单元，当存储在所述线程队列中的线程数超过等于或大于所述第一阈值的第二值时，所述电源恢复单元使得所述电源单元恢复向所述其他停止的处理器核心的电力供应。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式