专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08384160B2 Semiconductor device and method of manufacturing same 有权
公开(公告)号：US08384160B2
公开(公告)日：2013-02-26
申请号：US12627060
申请日：2009-11-30
申请人： Kazuhiro Onishi , Kazuhiro Tsukamoto
发明人： Kazuhiro Onishi , Kazuhiro Tsukamoto
IPC分类号： H01L21/70
CPC分类号： H01L21/823462 , G11C11/412 , H01L21/82345 , H01L27/11 , H01L27/1104 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage. The threshold voltage of a second nMIS transistor is greater than the threshold voltage of a first nMIS transistor and the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a second nMIS high-k film included in the second nMIS transistor is lower than the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a first nMIS high-k film included in the first nMIS transistor.

2. 发明申请

US20100164007A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100164007A1
公开(公告)日：2010-07-01
申请号：US12627060
申请日：2009-11-30
申请人： Kazuhiro ONISHI , Kazuhiro Tsukamoto
发明人： Kazuhiro ONISHI , Kazuhiro Tsukamoto
IPC分类号： H01L27/088 , H01L27/11 , H01L21/8234
CPC分类号： H01L21/823462 , G11C11/412 , H01L21/82345 , H01L27/11 , H01L27/1104 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage.The threshold voltage of a second nMIS transistor is greater than the threshold voltage of a first nMIS transistor and the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a second nMIS high-k film included in the second nMIS transistor is lower than the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a first nMIS high-k film included in the first nMIS transistor.
摘要翻译：为了提供一种半导体器件及其制造方法，当使用具有不同的阈值电压绝对值的多个MIS晶体管时，能够抑制阈值电压绝对值较大的MIS晶体管的驱动电流的降低。第二nMIS晶体管的阈值电压大于第一nMIS晶体管的阈值电压，并且包含在第二nMIS晶体管中的第二nMIS高k膜中的镧原子浓度与镁原子浓度之和较低比第一nMIS晶体管中包含的第一nMIS高k膜中的镧原子浓度和镁原子浓度的总和。

3. 发明授权

US06888245B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06888245B2
公开(公告)日：2005-05-03
申请号：US10222814
申请日：2002-08-19
申请人： Kazuhiro Tsukamoto
发明人： Kazuhiro Tsukamoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L27/108 , H01L29/40
CPC分类号： H01L21/76889 , H01L21/28518 , H01L23/485 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a conductive layer formed on a silicon semiconductor substrate, cobalt silicide films formed in a surface layer of the conductive layer, an interlayer insulating film which covers the silicon semiconductor substrate thereabove, and a barrier metal film and a tungsten film which fill in a contact hole formed in the interlayer insulating film and is electrically connected to the cobalt silicide film. The positions of lower surfaces of the cobalt silicide films at the bottom of the contact hole are set lower than the position of a lower surface of the cobalt silicide film provided outside the contact hole. A cobalt silicide film having a necessary thickness can be ensured at the bottom of the contact hole. Further, a contact resistance can be reduced and a junction leak can be suppressed.
摘要翻译：半导体器件包括形成在硅半导体衬底上的导电层，形成在导电层的表面层中的钴硅化物膜，覆盖其上面的硅半导体衬底的层间绝缘膜，以及阻挡金属膜和填充在形成在层间绝缘膜中并与硅化钴膜电连接的接触孔中。接触孔底部的硅化钴膜的下表面的位置被设定为低于设置在接触孔外侧的硅化钴膜的下表面的位置。可以在接触孔的底部确保具有必要厚度的硅化钴膜。此外，可以降低接触电阻并且可以抑制结泄漏。

4. 发明授权

US4934826A Block partitioned dynamic semiconductor memory device 失效
标题翻译：块分割动态半导体存储器件
公开(公告)号：US4934826A
公开(公告)日：1990-06-19
申请号：US211548
申请日：1988-06-24
申请人： Hideshi Miyatake , Hiroyuki Yamasaki , Masaki Shimoda , Kazuhiro Tsukamoto
发明人： Hideshi Miyatake , Hiroyuki Yamasaki , Masaki Shimoda , Kazuhiro Tsukamoto
IPC分类号： G11C11/406 , G11C11/408 , G11C11/409
CPC分类号： G11C11/409 , G11C11/406 , G11C11/408
摘要： A word line driving signal generating circuit and a sense amplifier activating signal generating circuit are provided for every partitioned memory cell array. When the levels of an external RAS signal and an external CAS signal have a predetermined relation and an external RNC signal remains at a predetermined potential or more, a refresh operation is started. A refresh address is generated from a refresh address counter in a sense restore control circuit. All of the memory cell arrays are simultaneously refreshed in response to the address. On this occasion, an operation for selecting a column by a column decoder provided in each of the memory cell arrays is inhibited. In the case in which an input of the external RNC signal is not prepared, when the levels of the external RAS signal and the external CAS signal have a predetermined relation and this state is held in a predetermined time period or more, the same refresh operation as described above is started.
摘要翻译：为每个分区存储单元阵列提供字线驱动信号发生电路和读出放大器激活信号产生电路。当外部RAS信号和外部CAS信号的电平具有预定关系并且外部RNC信号保持在预定电位或更大时，开始刷新操作。从感测恢复控制电路中的刷新地址计数器产生刷新地址。响应于地址，所有的存储单元阵列被同时刷新。在这种情况下，禁止通过设置在每个存储单元阵列中的列解码器来选择列的操作。在没有准备外部RNC信号的输入的情况下，当外部RAS信号和外部CAS信号的电平具有预定关系并且该状态保持在预定时间段或更长时间时，相同的刷新操作如上所述开始。

5. 发明授权

US07777280B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07777280B2
公开(公告)日：2010-08-17
申请号：US12263130
申请日：2008-10-31
申请人： Kazuhiro Tsukamoto
发明人： Kazuhiro Tsukamoto
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/823857 , H01L29/665
摘要： There have been provided a semiconductor device capable of preventing defects associated with etching, such as an increase in leak current, deterioration in film-coating properties and deterioration in transistor properties, and a method for manufacturing the semiconductor device. A CMOS transistor includes, on the same semiconductor substrate, an NMOS transistor having a gate electrode and a PMOS transistor having a gate electrode, wherein the former gate electrode includes a gate insulating film, a polycrystal silicon layer, a metal layer and another polycrystal silicon layer, and the latter gate electrode includes a gate insulating film, a metal layer and a polycrystal silicon layer.
摘要翻译：已经提供了能够防止与蚀刻相关的缺陷的半导体器件，例如泄漏电流的增加，膜包覆性能的劣化和晶体管特性的劣化，以及半导体器件的制造方法。 CMOS晶体管在相同的半导体衬底上包括具有栅电极和PMOS晶体管的NMOS晶体管，其具有栅电极，其中前栅电极包括栅极绝缘膜，多晶硅层，金属层和另一多晶硅并且后一栅电极包括栅极绝缘膜，金属层和多晶硅层。

6. 发明授权

US4843596A Semiconductor memory device with address transition detection and timing control 失效
标题翻译：具有地址转换检测和定时控制的半导体存储器件
公开(公告)号：US4843596A
公开(公告)日：1989-06-27
申请号：US124554
申请日：1987-11-24
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
IPC分类号： G11C11/401 , G11C7/22 , G11C8/18
CPC分类号： G11C8/18 , G11C7/22
摘要： A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.
摘要翻译：一种新颖的半导体存储器件包括响应于地址变化的检测而产生短宽度脉冲的地址检测电路。列解码器激活信号发生器检测短宽度脉冲的开始，并且响应于产生列解码器激活信号。第二检测电路检测短宽度脉冲的结论，并产生触发前置放大器激活信号的第二脉冲，其激活前置放大器并锁存输入/输出线上存在的数据。复位信号发生器产生复位信号以停用列解码器激活信号并延迟前置放大器激活信号。当输出第一个脉冲时，前置放大器激活信号发生器和复位信号发生器被复位。

7. 发明授权

US4823322A Dynamic random access memory device having an improved timing arrangement 失效
标题翻译：具有改进的定时布置的动态随机存取存储器件
公开(公告)号：US4823322A
公开(公告)日：1989-04-18
申请号：US102683
申请日：1987-09-30
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
IPC分类号： G11C11/407 , G11C11/401 , G11C11/4076 , G11C11/409 , G11C11/413 , G11C7/00
CPC分类号： G11C11/4076
摘要： A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.
摘要翻译：具有连接在一对输入/输出线之间的输入/输出负载和用于产生内部/ RAS信号的动态随机存取存储器件，该内部/ RAS信号具有相对于外部/ RAS信号的相同转变延迟的复位转变。内部/ RAS信号至少控制施加到所选择的存储单元的晶体管的字信号和施加到使能晶体管的使能信号，从而使存储器单元和使能晶体管变为不导通的时间被延迟相对于连接在每对位线和输入/输出线之间的传输晶体管的时间变得不导通。

8. 发明授权

US06483140B1 DRAM storage node with insulating sidewalls 失效
标题翻译：具有绝缘侧壁的DRAM存储节点
公开(公告)号：US06483140B1
公开(公告)日：2002-11-19
申请号：US09481387
申请日：2000-01-12
申请人： Takeru Matsuoka , Kazuhiro Tsukamoto
发明人： Takeru Matsuoka , Kazuhiro Tsukamoto
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10873 , H01L27/10888
摘要： A lower insulating film is formed so as to cover source/drain regions electrically connected to capacitors. Bit lines and upper insulating layers are formed on the lower insulating film. SCs opening to the lower insulating film are formed by an anisotropic etching process on process conditions for etching the upper insulating films at a high upper insulating film/lower insulating film selectivity. An insulating film of a quality equal to that of the lower insulating film is deposited so as to fill up the SCs and to cover the upper insulating film. The SCs is extended so as to open to the source/drain regions by an anisotropic etching process on process conditions for etching the lower insulating film at a high lower insulating film/silicon film selectivity.
摘要翻译：形成下绝缘膜以覆盖与电容器电连接的源极/漏极区域。位线和上绝缘层形成在下绝缘膜上。通过各向异性蚀刻工艺，以高上绝缘膜/下绝缘膜选择性蚀刻上绝缘膜的工艺条件形成通向下绝缘膜的SC。沉积质量等于下绝缘膜的绝缘膜，以填充SC并覆盖上绝缘膜。通过各向异性蚀刻工艺对SCs进行扩展，以在较低的绝缘膜/硅膜选择性下蚀刻下绝缘膜的工艺条件下对源/漏区开放。

9. 发明授权

US6025652A Semiconductor device and method of producing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6025652A
公开(公告)日：2000-02-15
申请号：US81680
申请日：1998-05-20
申请人： Kazuhiro Tsukamoto
发明人： Kazuhiro Tsukamoto
IPC分类号： H01L21/027 , H01L21/8242 , H01L27/108 , H01L23/544 , H01L23/48
CPC分类号： H01L27/10844 , H01L27/10852
摘要： In a semiconductor device having a mark opening portion such as an alignment mark and an overlay mark, a BPSG film formed by patterning on this mark opening portion interposing a first conductive film is covered by a second conductive film; and the BPSG film serves as a core of a cylindrical storage node and is removed after the second conductive film is formed in a shape of sidewall by a vapor phase HF treatment process, whereby a conductive contaminant is not peeled off at the time of removing the BPSG film, wherein a drop of yield can be restricted.
摘要翻译：在具有诸如对准标记和重叠标记的标记开口部分的半导体器件中，通过在插入第一导电膜的该标记开口部分上图案化形成的BPSG膜被第二导电膜覆盖; 并且BPSG膜用作圆柱形存储节点的核心，并且在通过气相HF处理工艺在第二导电膜形成为侧壁形状之后被去除，由此在去除导电性污染物时不会剥离导电性污染物 BPSG膜，其中可以限制一滴产率。

10. 发明授权

US5580813A Method of forming a semiconductor memory device having a contact region between memory cell and an interlayer insolating layer 失效
标题翻译：形成具有在存储单元与层间绝缘层之间的接触区域的半导体存储器件的方法
公开(公告)号：US5580813A
公开(公告)日：1996-12-03
申请号：US483037
申请日：1995-06-07
申请人： Atsushi Hachisuka , Kazuhiro Tsukamoto , Mitsuya Kinoshita
发明人： Atsushi Hachisuka , Kazuhiro Tsukamoto , Mitsuya Kinoshita
IPC分类号： H01L23/522 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10817
摘要： A portion of a cell plate 91 extending upon a field oxide film 107a and a silicon oxide film 123 is referred to as a lower layer interconnection film 109. The lower layer interconnection film 109 has a concave shape. A through hole 95a is formed in a silicon oxide film 93 reaching the bottom of the concave shape lower layer interconnection film 109. The depth of the through hole 95a is greater in comparison with the case where a through hole is formed on an upper face portion 123a of the silicon oxide film 123. Because the depth of through hole 95a is great, the thickness of the tungsten film 101a formed in through hole 95a becomes thicker. This eliminates the problem that all the tungsten film 101a in the through hole 95a, and then a portion of the lower layer interconnection film 109 are overetched. Therefore, electrical connection between the upper layer interconnection layer 103a and the lower layer interconnection layer 109 can be ensured.
摘要翻译：在场氧化膜107a和氧化硅膜123上延伸的单元板91的一部分被称为下层互连膜109.下层布线膜109具有凹形。在到达凹形下层互连膜109的底部的氧化硅膜93中形成通孔95a。与在上表面部分形成通孔的情况相比，通孔95a的深度更大 123a。由于通孔95a的深度大，所以形成在通孔95a中的钨膜101a的厚度变厚。这消除了通孔95a中的所有钨膜101a以及下层互连膜109的一部分被过蚀刻的问题。因此，可以确保上层布线层103a和下层布线层109之间的电连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式