会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • IMAGE FORMING APPARATUS
    • 图像形成装置
    • US20100196030A1
    • 2010-08-05
    • US12696283
    • 2010-01-29
    • Kazuhiro OkuboMasahiro YoshidaKazunori HashimotoMasahiro ShibataHisashi Yamauchi
    • Kazuhiro OkuboMasahiro YoshidaKazunori HashimotoMasahiro ShibataHisashi Yamauchi
    • G03G15/08
    • G03G15/08G03G15/0121G03G15/0173G03G15/0194G03G2215/0145
    • An image forming apparatus includes first and second developer carrying members and a control device. The apparatus is operable in a first mode where an image of a single color is formed using the first developer carrying member and is operable in a second mode, wherein an image of a plurality of colors is formed using the first and second developer carrying members. The control device controls a first discharging operation for discharging developer from the first developer carrying member and a second discharging operation for discharging developer from each of the first and second developer carrying members. When the apparatus executes only the first mode, the control device performs more image formations, in a period between completion of the second discharging operation and start of the first discharging operation, compared to a period between completion of the first discharging operation and start of a subsequent first discharging operation.
    • 图像形成装置包括第一和第二显影剂承载构件和控制装置。 该装置可以在第一模式中操作,其中使用第一显影剂承载构件形成单一颜色的图像,并且可以在第二模式下操作,其中使用第一和第二显影剂承载构件形成多种颜色的图像。 控制装置控制用于从第一显影剂承载构件排出显影剂的第一排出操作和用于从第一和第二显影剂承载构件中的每一个排出显影剂的第二排出操作。 当装置仅执行第一模式时,控制装置在第二次放电操作完成和第一次放电操作开始之间的时间段内,与第一次放电操作完成和第一次放电操作开始之间的时间段相比,执行更多的图像形成 后续第一次放电操作。
    • 4. 发明申请
    • IMAGE FORMING APPARATUS
    • 图像形成装置
    • US20100303486A1
    • 2010-12-02
    • US12791412
    • 2010-06-01
    • Masahiro ShibataMasahiro YoshidaKazunori HashimotoKazuhiro OkuboHisashi Yamauchi
    • Masahiro ShibataMasahiro YoshidaKazunori HashimotoKazuhiro OkuboHisashi Yamauchi
    • G03G15/08G03G15/00
    • G03G15/065G03G15/0808
    • An image forming apparatus includes a toner carrying member for supplying toner to the image bearing member to visualize the latent image; a rotatable toner supply member, contacted to the toner carrying member, for supplying the toner to the toner carrying member, the toner supply member including a surface foam layer; a voltage applying device for applying voltages to the toner carrying member and the toner supply member; a controller for controlling the voltage application apparatus such that A and B have a polarity which is the same as a regular charging polarity of the toner, where A=Vs2−Vd2; B=(Vs2−Vd2)−(Vs1−Vd1); Vd1 is a voltage applied to the toner carrying member during a period in which the latent image is visualized; Vs1 is a voltage applied to the toner supplying member during the period; vd2 is a voltage applied to the toner carrying member during at least a part of a period which is after the visualization of the latent image and before stoppage of rotation of the toner supplying member; and Vs2 is a voltage applied to the toner supplying member during the at least the part of the period.
    • 图像形成装置包括用于向图像承载部件供应调色剂以使潜像可视化的调色剂承载部件; 与所述调色剂承载构件接触的用于将调色剂供给到所述调色剂承载构件的可旋转调色剂供给构件,所述调色剂供给构件包括表面泡沫层; 电压施加装置,用于向调色剂承载构件和调色剂供应构件施加电压; 用于控制电压施加装置的控制器,使得A和B具有与调色剂的常规充电极性相同的极性,其中A = Vs2-Vd2; B =(Vs2-Vd2) - (Vs1-Vd1); Vd1是在潜像可视化的期间中施加到调色剂承载构件的电压; Vs1是在该期间施加到调色剂供给构件的电压; vd2是在潜像的可视化之后和在调色剂供给构件的停止转动之前的期间的至少一部分期间施加到调色剂承载构件的电压; Vs2是在该周期的至少一部分期间施加到调色剂供给部件的电压。
    • 7. 发明授权
    • Integrated circuit
    • 集成电路
    • US08238177B2
    • 2012-08-07
    • US12662040
    • 2010-03-29
    • Hisashi Yamauchi
    • Hisashi Yamauchi
    • G11C7/00
    • G11C17/18G11C17/16G11C17/165G11C29/44G11C29/4401G11C29/785G11C2029/4402
    • Provided is an integrated circuit including: multiple memory cells; a redundant memory having a function of repairing a defective cell included in the multiple memory cells by placing a corresponding fuse among multiple fuses into a first state; a fuse data conversion circuit that generates first information of a first defective cell based on position information of the fuse placed into the first state corresponding to the first defective cell having been repaired; a repair data generation circuit that generates, upon detection of a second defective cell as a result of a test for the multiple memory cells, repair information for repairing the second defective cell according to the first information and second information of the second defective cell; and a fuse state change circuit that places a predetermined fuse among the multiple fuses into the first state according to the repair information generated by the repair data generation circuit.
    • 提供了一种集成电路,包括:多个存储单元; 具有通过将多个保险丝之间的对应保险丝置于第一状态来修复包括在多个存储单元中的有缺陷单元的功能的冗余存储器; 熔丝数据转换电路,其根据与已修复的第一有缺陷单元对应的第一状态的熔丝的位置信息,生成第一缺陷单元的第一信息; 修复数据生成电路,根据所述第二有缺陷单元的第一信息和第二信息,在检测到作为所述多个存储单元的测试结果的第二缺陷单元的检测结果时,生成用于修复所述第二缺陷单元的修复信息; 以及保险丝状态改变电路,其根据由修复数据生成电路生成的修复信息,将多个保险丝内的规定的熔丝置于第一状态。
    • 8. 发明授权
    • Delay test system for normal circuit
    • 正常电路延时测试系统
    • US6128253A
    • 2000-10-03
    • US93381
    • 1998-06-08
    • Hisashi Yamauchi
    • Hisashi Yamauchi
    • G01R31/28G01R31/317G01R31/3185G01R31/319G04F8/00
    • G01R31/31858
    • A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the teat clock signal in the test mode. Consequently, a delay test is carried out by the use of a timing difference between an edge timing of the normal mode clock signal and an edge timing of the test clock signal.
    • 延迟测试系统包括电子电路,例如具有待测试部分的正常电路和多个触发器电路。 在这种情况下,每个触发器电路彼此串联连接,以对所述正常电路执行延迟测试。 此外,第一时钟输入端子连接到翻盖和正常电路以输入正常模式时钟信号。 此外,第二时钟输入端子连接到触发器电路和正常电路以输入测试时钟信号。 利用这种结构,数据信号的输入和输出操作与在正常模式下由正常模式时钟信号确定的边沿定时同步地执行,条件是测试时钟信号未被提供给第二时钟输入端 。 另一方面,在测试模式下,第一和第二时钟输入端子由正常模式时钟信号和乳头时钟信号分别驱动。 因此,通过使用正常模式时钟信号的边沿定时与测试时钟信号的边沿定时之间的定时差进行延迟测试。
    • 10. 发明授权
    • Delay test system for normal circuit
    • 正常电路延时测试系统
    • US06574169B1
    • 2003-06-03
    • US09631561
    • 2000-08-03
    • Hisashi Yamauchi
    • Hisashi Yamauchi
    • G04F800
    • G01R31/31858
    • A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the test clock signal in the test mode. Consequently, a delay test is carried out by the use of a timing difference between an edge timing of the normal mode clock signal and an edge timing of the test clock signal.
    • 延迟测试系统包括电子电路,例如具有待测试部分的正常电路和多个触发器电路。 在这种情况下,每个触发器电路彼此串联连接,以对所述正常电路执行延迟测试。 此外,第一时钟输入端子连接到翻盖和正常电路以输入正常模式时钟信号。 此外,第二时钟输入端子连接到触发器电路和正常电路以输入测试时钟信号。 利用这种结构,数据信号的输入和输出操作与在正常模式下由正常模式时钟信号确定的边沿定时同步地执行,条件是测试时钟信号未被提供给第二时钟输入端 。 另一方面,在测试模式下,第一和第二时钟输入端分别由正常模式时钟信号和测试时钟信号驱动。 因此,通过使用正常模式时钟信号的边沿定时与测试时钟信号的边沿定时之间的定时差进行延迟测试。