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1. 发明授权

US08593443B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US08593443B2
公开(公告)日：2013-11-26
申请号：US13061545
申请日：2009-07-07
申请人： Kazuhiro Maeda , Ichiro Shiraki , Hiroaki Sugiyama
发明人： Kazuhiro Maeda , Ichiro Shiraki , Hiroaki Sugiyama
IPC分类号： G06F3/038
CPC分类号： G06F3/0412 , G02F2001/13312 , G09G3/3648 , G09G3/3688 , G09G2360/144 , G09G2360/148
摘要： A display device includes a photosensor (81) in a pixel region (1) of an active matrix substrate (100). The photosensor (81) includes a photodetection element, reset signal wiring that supplies a reset signal RS to the photosensor (81), readout signal wiring that supplies a readout signal RW to the photosensor (81), and a sensor switching element for reading out the potential of the storage node to output wiring as sensor circuit output, the potential of the storage node having changed in accordance with the amount of light received by the photodetection element in a sensing period, the sensing period being from when the reset signal is supplied until when the readout signal is supplied. The potential of wiring having a parasitic capacitance with the storage node is fixed to a predetermined potential V0 at least either one of immediately before the readout signal RW and immediately before the reset signal RS.
摘要翻译：显示装置包括在有源矩阵基板（100）的像素区域（1）中的光电传感器（81）。光传感器（81）包括光检测元件，向光传感器（81）提供复位信号RS的复位信号布线，向光电传感器（81）提供读出信号RW的读出信号布线和用于读出的传感器开关元件存储节点输出布线作为传感器电路输出的电位，存储节点的电位根据在感测周期中由光电检测元件接收的光量而改变，感测周期是从复位信号提供时直到提供读出信号为止。具有与存储节点的寄生电容的布线的电位在紧接在读出信号RW之前和紧接在复位信号RS之前的至少一个中固定到预定电位V0。

2. 发明申请

US20110157116A1 DISPLAY DEVICE 审中-公开
标题翻译：显示设备
公开(公告)号：US20110157116A1
公开(公告)日：2011-06-30
申请号：US13059161
申请日：2009-06-09
申请人： Ichiro Shiraki , Kazuhiro Maeda , Hiroaki Sugiyama
发明人： Ichiro Shiraki , Kazuhiro Maeda , Hiroaki Sugiyama
IPC分类号： G06F3/038
CPC分类号： G09G3/3648 , G09G2320/0233 , G09G2360/145 , H01L31/145
摘要： Provided is a display device including a sensor row driver (6) which sequentially outputs a read-out signal (RW) for causing each pair of picture element area groups, which includes both a first picture element area (PIX1) and a second picture element area (PIX2) as detection picture element areas and is made up of two picture element rows, to simultaneously output a photodetection signal of each of the first picture element areas (PIX1) and a dark current detection signal of each of the second picture element areas (PIX2). In each pair of the picture element area groups, outputs of the detection picture element areas are connected to different output lines (RSL1, RSL2).
摘要翻译：提供了一种显示装置，其包括传感器行驱动器（6），其顺序地输出用于使每对图像元素区域组的读出信号（RW），其包括第一图像元素区域（PIX1）和第二图像元素区域（PIX2）作为检测图像元素区域，并且由两个图像元素行构成，以同时输出第一像素区域（PIX1）中的每一个的每个的第一像素区域和第二像素区域的暗电流检测信号（PIX2）。在每对像素区域组中，检测像素区域的输出连接到不同的输出线（RSL1，RSL2）。

3. 发明申请

US20110149174A1 DISPLAY DEVICE 有权
标题翻译：显示设备
公开(公告)号：US20110149174A1
公开(公告)日：2011-06-23
申请号：US13061545
申请日：2009-07-07
申请人： Kazuhiro Maeda , Ichiro Shiraki , Hiroaki Sugiyama
发明人： Kazuhiro Maeda , Ichiro Shiraki , Hiroaki Sugiyama
IPC分类号： H04N5/66 , G09G5/00
CPC分类号： G06F3/0412 , G02F2001/13312 , G09G3/3648 , G09G3/3688 , G09G2360/144 , G09G2360/148
摘要： A display device includes a photosensor (81) in a pixel region (1) of an active matrix substrate (100). The photosensor (81) includes a photodetection element, reset signal wiring that supplies a reset signal RS to the photosensor (81), readout signal wiring that supplies a readout signal RW to the photosensor (81), and a sensor switching element for reading out the potential of the storage node to output wiring as sensor circuit output, the potential of the storage node having changed in accordance with the amount of light received by the photodetection element in a sensing period, the sensing period being from when the reset signal is supplied until when the readout signal is supplied. The potential of wiring having a parasitic capacitance with the storage node is fixed to a predetermined potential V0 at least either one of immediately before the readout signal RW and immediately before the reset signal RS.
摘要翻译：显示装置包括在有源矩阵基板（100）的像素区域（1）中的光电传感器（81）。光传感器（81）包括光检测元件，向光传感器（81）提供复位信号RS的复位信号布线，向光电传感器（81）提供读出信号RW的读出信号布线和用于读出的传感器开关元件存储节点输出布线作为传感器电路输出的电位，存储节点的电位根据在感测周期中由光电检测元件接收的光量而改变，感测周期是从复位信号提供时直到提供读出信号为止。具有与存储节点的寄生电容的布线的电位在紧接在读出信号RW之前和紧接在复位信号RS之前的至少一个中固定到预定电位V0。

4. 发明申请

US20110181568A1 DISPLAY DEVICE 审中-公开
标题翻译：显示设备
公开(公告)号：US20110181568A1
公开(公告)日：2011-07-28
申请号：US13120428
申请日：2009-06-09
申请人： Hiroaki Sugiyama , Kazuhiro Maeda , Ichiro Shiraki
发明人： Hiroaki Sugiyama , Kazuhiro Maeda , Ichiro Shiraki
IPC分类号： G06F3/038
CPC分类号： G09G3/3648 , G02F1/13318 , G02F1/1354 , G02F1/136286 , G02F2001/13312 , G06F3/0412 , G06F3/042
摘要： Outside provision of first row lines (CS(1) and CS(2)) is identical between a first picture element row (R1) and a second picture element row (R2) of each picture element row pair (20) in terms of whether each first row line is provided, with respect to picture element electrodes (ER(1), EG(1), EB(1), ER(2), EG(2), and EB(2)), so as to be closer to a photosensor circuit (SC) or farther from the photosensor circuit (SC).
摘要翻译：第一行线（CS（1）和CS（2））的外部设置在每个像素行对（20）的第一图像元素行（R1）和第二图像元素行（R2）之间是否相同相对于图像元素电极（ER（1），EG（1），EB（1），ER（2），EG（2）和EB（2））提供每个第一行线，以便更靠近光电传感器电路（SC）或离光电传感器电路（SC）更远。

5. 发明申请

US20100033458A1 Buffer circuit having voltage switching function, and liquid crystal display device 审中-公开
标题翻译：具有电压切换功能的缓冲电路和液晶显示装置
公开(公告)号：US20100033458A1
公开(公告)日：2010-02-11
申请号：US12311978
申请日：2007-07-05
申请人： Shinsaku Shimizu , Kazuhiro Maeda , Ichiro Shiraki
发明人： Shinsaku Shimizu , Kazuhiro Maeda , Ichiro Shiraki
IPC分类号： G09G5/00 , H03K17/00
CPC分类号： H03K5/08 , G09G3/3614 , G09G3/3688 , G09G3/3696 , G09G2310/027 , G09G2310/0291 , H03K5/22
摘要： In one embodiment of the invention, a capacitor is provided between a node and a negative-side input terminal of a differential amplifier. A switch SW11 is provided between the negative-side input terminal and an output terminal of the differential amplifier. A switch SW12 is provided between the node and the output terminal of the differential amplifier. Switches SW13 to SW16 are provided for switching between a voltage of the node and a positive-side input voltage of the differential amplifier. The switches SW11 and SW12 are on during different periods. In a positive polarity mode, the switches SW13 and SW16 are when the switch SW11 is on while the switch SW16 is on when the switch SW12 is on. In a negative polarity mode, the switches SW14 and SW15 are on when the switch SW11 is on while the switch SW16 is on when the switch SW12 is on. Thus, two types of gradation voltages each required for AC drive of a liquid crystal can be generated with a small circuit scale.
摘要翻译：在本发明的一个实施例中，在差分放大器的节点和负侧输入端之间提供电容器。开关SW11设置在差分放大器的负侧输入端子和输出端子之间。开关SW12设置在差分放大器的节点和输出端子之间。提供开关SW13至SW16用于在节点的电压和差分放大器的正侧输入电压之间切换。开关SW11和SW12在不同的周期内接通。在正极性模式中，开关SW13和SW16是当开关SW12导通时开关SW11导通的状态。在负极性模式下，当开关SW12导通时，开关SW11接通时，开关SW14，SW15接通。因此，可以以小的电路规模产生用于液晶的AC驱动所需的两种类型的灰度电压。

6. 发明申请

US20100259565A1 MONOLITHIC DRIVER-TYPE DISPLAY DEVICE 有权
标题翻译：单片驱动器型显示器件
公开(公告)号：US20100259565A1
公开(公告)日：2010-10-14
申请号：US12733884
申请日：2008-06-19
申请人： Yousuke Nakagawa , Kazuhiro Maeda , Ichiro Shiraki , Shuji Nishi , Sachio Tsujino
发明人： Yousuke Nakagawa , Kazuhiro Maeda , Ichiro Shiraki , Shuji Nishi , Sachio Tsujino
IPC分类号： G09G5/10
CPC分类号： G09G3/20 , G02F1/13454 , G02F1/1368 , G02F2001/13606 , G09G3/3685 , G09G2310/0275 , G09G2310/0297 , G09G2330/021 , H01L27/124
摘要： The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal.In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.
摘要翻译：本发明的目的在于提供一种能够降低采样电路的电路规模的单片驱动型显示装置，并且通过用外部提供的视频信号直接驱动源极驱动器来保持低功耗。在具有用于显示视频的显示部分和用于驱动形成在同一绝缘基板上的显示部分的电路的单片驱动型显示装置中，与外部输入的多个位数据相关联地提供多个采样开关数字视频信号。采样开关基于采样信号进行开/关，从而针对每一位数据采样数字视频信号，并将信号转换为并行格式以输出到数据线。输出的数字视频信号对数据线上的寄生电容进行充电并保持在其中。

7. 发明授权

US08305315B2 Monolithic driver-type display device 有权
标题翻译：单片驱动型显示装置
公开(公告)号：US08305315B2
公开(公告)日：2012-11-06
申请号：US12733884
申请日：2008-06-19
申请人： Yousuke Nakagawa , Kazuhiro Maeda , Ichiro Shiraki , Shuji Nishi , Sachio Tsujino
发明人： Yousuke Nakagawa , Kazuhiro Maeda , Ichiro Shiraki , Shuji Nishi , Sachio Tsujino
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G02F1/13454 , G02F1/1368 , G02F2001/13606 , G09G3/3685 , G09G2310/0275 , G09G2310/0297 , G09G2330/021 , H01L27/124
摘要： The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal.In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.
摘要翻译：本发明的目的在于提供一种能够降低采样电路的电路规模的单片驱动型显示装置，并且通过用外部提供的视频信号直接驱动源极驱动器来保持低功耗。在具有用于显示视频的显示部分和用于驱动形成在同一绝缘基板上的显示部分的电路的单片驱动型显示装置中，与外部输入的多个位数据相关联地提供多个采样开关数字视频信号。采样开关基于采样信号进行开/关，从而针对每一位数据采样数字视频信号，并将信号转换为并行格式以输出到数据线。输出的数字视频信号对数据线上的寄生电容进行充电并保持在其中。

8. 发明授权

US07196699B1 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行
公开(公告)号：US07196699B1
公开(公告)日：2007-03-27
申请号：US09506033
申请日：2000-02-16
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G5/00 , G09G3/26 , H03K19/0175 , H03K19/00 , H03K5/153
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

9. 发明申请

US20050057556A1 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行
公开(公告)号：US20050057556A1
公开(公告)日：2005-03-17
申请号：US10949990
申请日：2004-09-23
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

10. 发明授权

US08068190B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US08068190B2
公开(公告)日：2011-11-29
申请号：US13061603
申请日：2009-06-02
申请人： Kazuhiro Maeda , Ichiro Shiraki , Hiromi Katoh , Kouji Kumada
发明人： Kazuhiro Maeda , Ichiro Shiraki , Hiromi Katoh , Kouji Kumada
IPC分类号： G02F1/136
CPC分类号： G06F3/042 , G06F3/0412 , H01L27/14643
摘要： In a photosensor in the pixel region of an active matrix substrate, the potential of a storage node is read out to output wiring as sensor circuit output, the potential of the storage node having changed in accordance with the amount of light received by a photodetection element in a sensing period, the sensing period being from when a reset signal (RS) is supplied until when a readout signal (RW) is supplied. A sensor startup period whose length is greater than or equal to the length of the sensing period is provided after a sensor data unnecessary period in which the sensor circuit output is not necessary, and furthermore before a valid sensor data period in which the sensor circuit output is necessary, and the sensor circuit output is read out in the valid sensor data period from the photosensor to which the reset signal was applied in the sensor startup period.
摘要翻译：在有源矩阵基板的像素区域中的光电传感器中，读出存储节点的电位以输出布线作为传感器电路输出，存储节点的电位根据由光检测元件接收的光量而变化在感测周期中，感测周期是从提供复位信号（RS）直到提供读出信号（RW）时。在不需要传感器电路输出的传感器数据不必要的周期之后，并且在传感器电路输出的有效传感器数据周期之前，提供长度大于或等于感测周期的长度的传感器启动周期是必要的，并且传感器电路输出在有效传感器数据周期中从传感器启动周期中应用复位信号的光电传感器读出。

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