专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4575925A Method for fabricating a SOI type semiconductor device 失效
标题翻译： SOI型半导体器件的制造方法
公开(公告)号：US4575925A
公开(公告)日：1986-03-18
申请号：US675613
申请日：1984-11-28
申请人： Kazuhiro Kanbara , Osamu Hataishi
发明人： Kazuhiro Kanbara , Osamu Hataishi
IPC分类号： H01L21/20 , H01L21/74 , H01L21/86 , H01L21/324 , H01L21/36
CPC分类号： H01L21/743 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02639 , H01L21/86 , Y10S148/05
摘要： A method for fabricating a connection to a deep buried layer of a bipolar transistor based on SOI technology. In such a method, an epitaxial layer is grown on a single crystalline island formed by recrystallizing a polycrystalline layer on an insulating layer. Then the side surface(s) of the epitaxial layer is tentatively exposed and a conduction path along the side surface(s) is formed extending from the upper surface of the epitaxial layer to the single crystalline island thereunder.
摘要翻译：基于SOI技术制造与双极晶体管的深埋层的连接的方法。在这种方法中，通过在绝缘层上重结晶多晶层而形成的单晶岛上生长外延层。然后暂时露出外延层的侧表面，并且形成沿着侧表面的传导路径，其从外延层的上表面延伸到其下面的单晶岛。

2. 发明授权

US4629520A Method of forming shallow n-type region with arsenic or antimony and phosphorus 失效
标题翻译：用砷或锑和磷形成浅的n型区域的方法
公开(公告)号：US4629520A
公开(公告)日：1986-12-16
申请号：US640577
申请日：1984-08-14
申请人： Katsunobu Ueno , Osamu Hataishi
发明人： Katsunobu Ueno , Osamu Hataishi
IPC分类号： H01L29/73 , H01L21/22 , H01L21/225 , H01L21/331 , H01L29/72 , H01L21/385 , H01L21/425
CPC分类号： H01L29/72 , H01L21/22 , H01L21/2257
摘要： A method of forming a shallow n-type region of a semiconductor device, such as a bipolar transistor or a MOS FET, includes the following steps. Forming a first film containing arsenic or antimony on a silicon substrate; forming a second film containing phosphorus on the first film; and diffusing the arsenic or antimony and the phosphorus into the semiconductor substrate out of the first and second films by heat-treatment. The diffused impurities of the arsenic or antimony and the phosphorus form the n-type region and the arsenic or antimony defines the depth of the n-type region.
摘要翻译：形成诸如双极晶体管或MOS FET的半导体器件的浅n型区域的方法包括以下步骤。在硅衬底上形成含有砷或锑的第一层膜; 在所述第一膜上形成含磷的第二膜; 并且通过热处理将砷或锑和磷扩散到第一和第二膜中的半导体衬底内。砷或锑和磷的扩散杂质形成n型区域，砷或锑限定n型区域的深度。

3. 发明授权

US4231057A Semiconductor device and method for its preparation 失效
标题翻译：半导体器件及其制备方法
公开(公告)号：US4231057A
公开(公告)日：1980-10-28
申请号：US960228
申请日：1978-11-13
申请人： Yoshinobu Momma , Yunosuke Kawabe , Osamu Hataishi
发明人： Yoshinobu Momma , Yunosuke Kawabe , Osamu Hataishi
IPC分类号： H01L21/76 , H01L21/761 , H01L21/763 , H01L27/04
CPC分类号： H01L21/761 , H01L21/76 , H01L21/763
摘要： An improved means and method for isolating semiconductor devices on a semiconductor substrate, comprising a shallow region formed between the semiconductor substrate and an epitaxial layer of each device, and between a buried layer of each device and an isolation region separating adjacent devices. The shallow region has conductivity type opposite to that of the semiconductor substrate and higher impurity concentration than that of the epitaxial layer.
摘要翻译：一种用于隔离半导体衬底上的半导体器件的改进方法和方法，包括形成在每个器件的半导体衬底和外延层之间以及在每个器件的掩埋层与分离相邻器件的隔离区之间形成的浅区域。浅区域具有与半导体衬底的导电类型相反的导电类型和比外延层的杂质浓度更高的杂质浓度。

4. 发明授权

US4584025A Process for fabricating a semiconductor on insulator semiconductor device 失效
标题翻译：半导体绝缘体半导体器件的制造方法
公开(公告)号：US4584025A
公开(公告)日：1986-04-22
申请号：US674831
申请日：1984-11-26
申请人： Matsuo Takaoka , Nobuo Sasaki , Seiichiro Kawamura , Osamu Hataishi
发明人： Matsuo Takaoka , Nobuo Sasaki , Seiichiro Kawamura , Osamu Hataishi
IPC分类号： H01L27/00 , H01L21/20 , H01L21/268 , H01L21/3215 , H01L21/74 , H01L21/762 , H01L21/86 , H01L21/388
CPC分类号： H01L21/86 , H01L21/0242 , H01L21/02532 , H01L21/02636 , H01L21/02675 , H01L21/268 , H01L21/32155 , H01L21/74 , H01L21/76264 , H01L21/76283 , Y10S117/904
摘要： A process for fabricating a substrate having a dielectrically isolated region, using energy beam recrystallization. An island of polysilicon is formed on an insulating substrate and a cap containing a dopant is coated on the entire surface of the substrate. A laser beam is irradiated through the cap, and the polysilicon is recrystallized to form a doped first single crystal silicon layer. A second single crystal silicon layer is grown over the first single crystal layer. The first single crystal layer is used as a buried layer, and a semiconductor device is fabricated in the second single crystal layer. This process avoids the existence of crystal imperfections at the boundaries of the single crystal layers.
摘要翻译：一种使用能量束重结晶制造具有介电隔离区域的衬底的工艺。在绝缘基板上形成多晶硅岛，并且在基板的整个表面上涂覆含有掺杂剂的盖。通过盖子照射激光束，并且多晶硅被重结晶以形成掺杂的第一单晶硅层。在第一单晶层上生长第二单晶硅层。第一单晶层用作掩埋层，并且在第二单晶层中制造半导体器件。该过程避免了在单晶层边界存在晶体缺陷。

5. 发明授权

US4376664A Method of producing a semiconductor device 失效
标题翻译：半导体装置的制造方法
公开(公告)号：US4376664A
公开(公告)日：1983-03-15
申请号：US155124
申请日：1980-05-30
申请人： Osamu Hataishi , Yoshinobu Momma
发明人： Osamu Hataishi , Yoshinobu Momma
IPC分类号： H01L21/76 , H01L21/20 , H01L21/26
CPC分类号： H01L21/76
摘要： In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermal-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal oxidation. Prior to a step of introducing impurities into the epitaxial layer, the epitaxial layer is covered by an anti-oxidation masking layer, an insulating layer and a photo resist layer. Subsequent to the step of introducing impurities, the anti-oxidation masking layer is shaped into a pattern mask for the thermal-oxidation treatment.
摘要翻译：在制造包括至少一个半导体元件的半导体器件，围绕半导体元件的隔离区域和位于半导体元件周围和周围的厚氧化硅层的情况下，通过热氧化外延层形成厚氧化物层具有掩埋层，并且同时通过加热进行热氧化而在外延层中形成隔离区。在将杂质引入外延层的步骤之前，外延层被抗氧化屏蔽层，绝缘层和光致抗蚀剂层覆盖。在引入杂质的步骤之后，将抗氧化掩模层成型为用于热氧化处理的图案掩模。

6. 发明授权

US4875085A Semiconductor device with shallow n-type region with arsenic or antimony and phosphorus 失效
标题翻译：半导体器件具有浅的n型区域，具有砷或锑和磷
公开(公告)号：US4875085A
公开(公告)日：1989-10-17
申请号：US195468
申请日：1988-05-17
申请人： Katsunobu Ueno , Osamu Hataishi
发明人： Katsunobu Ueno , Osamu Hataishi
IPC分类号： H01L29/73 , H01L21/22 , H01L21/225 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72 , H01L21/22 , H01L21/2257
摘要： A method of forming a shallow n-type region of a semiconductor device such as a bipolar transistor and a MOS FET, including the steps of: forming a first film containing arsenic or antimony on a silicon substrate; forming a second film containing phosphorus on the first film; and diffusing the arsenic or antimony and the phosphorus into the semiconductor substrate out of the first and second films by heat-treatment. The diffused impurities of the arsenic or antimony and the phosphorus form the n-type region and the arsenic or antimony defines the depth of the n-type region.

7. 再颁专利

USRE31937E Semiconductor device and method for its preparation 失效
标题翻译：半导体器件及其制备方法
公开(公告)号：USRE31937E
公开(公告)日：1985-07-02
申请号：US240498
申请日：1981-03-04
申请人： Yoshinobu Momma , Yunosuke Kawabe , Osamu Hataishi
发明人： Yoshinobu Momma , Yunosuke Kawabe , Osamu Hataishi
IPC分类号： H01L21/76 , H01L21/761 , H01L21/763
CPC分类号： H01L21/76 , H01L21/761 , H01L21/763
摘要： An improved means and method for isolating semiconductor devices on a semiconductor substrate, comprising a shallow region formed between the semiconductor substrate and an epitaxial layer of each device, and between a buried layer of each device and an isolation region separating adjacent devices. The shallow region has conductivity type opposite to that of the semiconductor substrate and higher impurity concentration than that of the epitaxial layer.

8. 再颁专利

USRE31652E Method of producing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：USRE31652E
公开(公告)日：1984-08-28
申请号：US527498
申请日：1983-08-29
申请人： Osamu Hataishi , Yoshinobu Momma , Ryoji Abe
发明人： Osamu Hataishi , Yoshinobu Momma , Ryoji Abe
IPC分类号： H01L21/316 , H01L21/331 , H01L21/76 , H01L29/73
CPC分类号： H01L21/76
摘要： In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermally-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal oxidation. Prior to a step of introducing impurities into the epitaxial layer, a patterned thin silicon oxide layer is formed. This thin silicon oxide layer is varied into the thick oxide layer by the thermal-oxidation treatment.

9. 发明授权

US4343080A Method of producing a semiconductor device 失效
标题翻译：半导体装置的制造方法
公开(公告)号：US4343080A
公开(公告)日：1982-08-10
申请号：US155122
申请日：1980-05-30
申请人： Osamu Hataishi , Yoshinobu Momma , Ryoji Abe
发明人： Osamu Hataishi , Yoshinobu Momma , Ryoji Abe
IPC分类号： H01L21/316 , H01L21/331 , H01L21/76 , H01L29/73 , H01L21/22
CPC分类号： H01L21/76
摘要： In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermally-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal oxidation. Prior to a step of introducing impurities into the epitaxial layer, a patterned thin silicon oxide layer is formed. This thin silicon oxide layer is varied into the thick oxide layer by the thermal-oxidation treatment.
摘要翻译：在制造包括至少一个半导体元件，围绕半导体元件的隔离区域和位于半导体元件周围和周围的厚氧化硅层的半导体器件的情况下，通过热氧化外延层形成厚氧化物层具有掩埋层，并且同时通过加热进行热氧化而在外延层中形成隔离区。在将杂质引入外延层的步骤之前，形成图案化的氧化硅薄层。该氧化硅薄层通过热氧化处理变成厚氧化物层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式