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1. 发明授权

US5952712A Packaged semiconductor device and method of manufacturing the same 失效
公开(公告)号：US5952712A
公开(公告)日：1999-09-14
申请号：US893988
申请日：1997-07-16
申请人： Kazuhiro Ikuina , Yuzo Shimada , Kazuaki Utsumi
发明人： Kazuhiro Ikuina , Yuzo Shimada , Kazuaki Utsumi
IPC分类号： H01L23/12 , H01L21/60 , H01L21/768 , H01L23/13 , H01L23/48 , H01L23/02
CPC分类号： H01L24/80 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15787
摘要： A packaged semiconductor device includes an LSI chip, a chip size package integrally bonded to the LSI chip to mount and hold the LSI chip thereon in order to connect an electrode of a board on which the LSI chip is to be mounted and an electrode of the LSI chip to each other, an electrode formed on a surface of the package opposite to a surface thereof which is bonded to the LSI chip, so as to be connected to the electrode of the board, at least one through hole formed to extend through the LSI chip and the package, and a connecting conductor formed to extend through the through hole in order to connect the electrode of the package and the electrode of the LSI package to each other.

2. 发明授权

US6130111A Packaged semiconductor device and method of manufacturing the same 有权
标题翻译：封装半导体器件及其制造方法
公开(公告)号：US6130111A
公开(公告)日：2000-10-10
申请号：US333578
申请日：1999-06-15
申请人： Kazuhiro Ikuina , Yuzo Shimada , Kazuaki Utsumi
发明人： Kazuhiro Ikuina , Yuzo Shimada , Kazuaki Utsumi
IPC分类号： H01L23/12 , H01L21/60 , H01L21/768 , H01L23/13 , H01L23/48 , H01L21/44
CPC分类号： H01L24/80 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15787
摘要： A packaged semiconductor device includes an LSI chip, a chip size package integrally bonded to the LSI chip to mount and hold the LSI chip thereon in order to connect an electrode of a board on which the LSI chip is to be mounted and an electrode of the LSI chip to each other, an electrode formed on a surface of the package opposite to a surface thereof which is bonded to the LSI chip, so as to be connected to the electrode of the board, at least one through hole formed to extend through the LSI chip and the package, and a connecting conductor formed to extend through the through hole in order to connect the electrode of the package and the electrode of the LSI package to each other.
摘要翻译：封装半导体器件包括：LSI芯片，与LSI芯片整体接合的芯片尺寸封装，以将LSI芯片安装和保持在其上，以便将要安装LSI芯片的板的电极和 LSI芯片彼此之间形成有与其与LSI芯片接合的表面的与其表面相反的表面形成的电极，以与板的电极连接，至少一个通孔形成为延伸通过 LSI芯片和封装，以及形成为延伸穿过通孔的连接导体，以将封装的电极和LSI封装的电极彼此连接。

3. 发明授权

US5753376A Multilayer glass ceramic substrate and process for producing the same 失效
公开(公告)号：US5753376A
公开(公告)日：1998-05-19
申请号：US846820
申请日：1997-04-30
申请人： Kazuhiro Ikuina , Yuzo Shimada
发明人： Kazuhiro Ikuina , Yuzo Shimada
IPC分类号： C03C14/00 , C03C17/36 , H01L23/15 , B32B15/04
CPC分类号： C03C17/361 , C03C14/004 , C03C17/36 , C03C17/3639 , C03C17/3642 , H01L23/15 , C03C2214/04 , H01L2924/0002 , H01L2924/09701 , Y10S428/901 , Y10T428/24851 , Y10T428/24917 , Y10T428/24926
摘要： A multilayer glass ceramic substrate having a plurality of conductor layers each laminated through a glass ceramic layer. The glass ceramic layer has a composition comprising of alumina, borosilicate magnesium glass and cordierite crystal produced by chemical reaction between alumina and borosilicate magnesium glass. The content of alumina is 12 to 59.6 wt %, the content of borosilicate magnesium glass is 18 to 69.6 wt %, the content of the cordierite crystal is 1 to 50 wt % and the sum of components is 100 wt %. The multilayer glass ceramic substrate shows improved mechanical strength.

4. 发明授权

US5989484A Multilayer glass ceramic substrate and process for producing the same 失效
标题翻译：多层玻璃陶瓷基板及其制造方法
公开(公告)号：US5989484A
公开(公告)日：1999-11-23
申请号：US998292
申请日：1997-12-24
申请人： Kazuhiro Ikuina , Yuzo Shimada
发明人： Kazuhiro Ikuina , Yuzo Shimada
IPC分类号： C03C14/00 , C03C17/36 , H01L23/15 , B32B17/02
CPC分类号： C03C17/361 , C03C14/004 , C03C17/36 , C03C17/3639 , C03C17/3642 , H01L23/15 , C03C2214/04 , H01L2924/0002 , H01L2924/09701 , Y10S428/901 , Y10T428/24851 , Y10T428/24917 , Y10T428/24926
摘要： A multilayer glass ceramic substrate having a plurality of conductor layers each laminated through a glass ceramic layer. The glass ceramic layer has a composition comprising of alumina, borosilicate magnesium glass and cordierite crystal produced by chemical reaction between alumina and borosilicate magnesium glass. The content of alumina is 12 to 59.6 wt %, the content of borosilicate magnesium glass is 18 to 69.6 wt %, the content of the cordierite crystal is 1 to 50 wt % and the sum of components is 100 wt %. The multilayer glass ceramic substrate shows improved mechanical strength.
摘要翻译：一种多层玻璃陶瓷基板，具有通过玻璃陶瓷层层叠的多个导体层。玻璃陶瓷层具有由氧化铝，硼硅酸镁玻璃和氧化铝与硼硅酸镁玻璃之间的化学反应制造的堇青石晶体的组成。氧化铝的含量为12〜59.6重量％，硼硅酸镁玻璃的含量为18〜69.6重量％，堇青石结晶的含量为1〜50重量％，成分总量为100重量％。多层玻璃陶瓷基板显示出改进的机械强度。

5. 发明授权

US06188127B1 Semiconductor packing stack module and method of producing the same 失效
标题翻译：半导体封装堆叠模块及其制造方法
公开(公告)号：US06188127B1
公开(公告)日：2001-02-13
申请号：US08604115
申请日：1996-02-20
申请人： Naoji Senba , Yuzo Shimada , Kazuaki Utsumi , Kenichi Tokuno , Ikushi Morizaki , Akihiro Dohya , Manabu Bonkohara
发明人： Naoji Senba , Yuzo Shimada , Kazuaki Utsumi , Kenichi Tokuno , Ikushi Morizaki , Akihiro Dohya , Manabu Bonkohara
IPC分类号： H01L2302
CPC分类号： H01L24/28 , H01L21/563 , H01L25/105 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48247 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/83102 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15331 , H01L2924/15787 , H01L2924/1627 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/3011 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/0665 , H01L2924/00012
摘要： In a semiconductor package stack module, an LSI (Large Scale Integrated circuit) is mounted, via fine bumps, on a ceramic carrier substrate or a flexible carrier film on which wiring conductors are formed. After a seal resin has been injected, the chip is thinned by, e.g., grinding. A plurality of such carrier substrates or carrier films are connected to each other by bumps via through holes which are electrically connected to the wiring conductors, thereby completing a tridimensional stack module. The module achieves a miniature, thin, dense, low cost, and reliable structure without resorting to a wire bonding system or a TAB (Tape Automated Bonding) system. In addition, the module has a minimum of wiring length and a desirable electric characteristic.
摘要翻译：在半导体封装堆叠模块中，通过微小的凸块将LSI（大规模集成电路）安装在陶瓷载体基板或形成布线导体的柔性载体膜上。在注入密封树脂之后，通过例如研磨使芯片变薄。多个这样的载体基板或载体膜通过与导线导电连接的通孔而由凸块彼此连接，从而完成三维叠层模块。该模块实现了微型，薄型，致密，低成本和可靠的结构，而不需要使用引线接合系统或TAB（磁带自动接合）系统。此外，该模块具有最小的布线长度和期望的电特性。

6. 发明授权

US5830563A Interconnection structures and method of making same 失效
标题翻译：互连结构及其制作方法
公开(公告)号：US5830563A
公开(公告)日：1998-11-03
申请号：US752798
申请日：1996-11-20
申请人： Tadanori Shimoto , Yoshitsugu Funada , Koji Matsui , Yuzo Shimada , Kazuaki Utsumi
发明人： Tadanori Shimoto , Yoshitsugu Funada , Koji Matsui , Yuzo Shimada , Kazuaki Utsumi
IPC分类号： H05K1/00 , H05K3/00 , H05K3/18 , H05K3/46 , B32B3/00
CPC分类号： H05K3/4661 , H05K3/465 , H05K2201/0195 , H05K2201/0355 , H05K2201/0394 , H05K3/0023 , H05K3/184 , H05K3/4676 , Y10S428/901 , Y10T428/24917 , Y10T428/3154
摘要： This invention relates to an interconnection structure comprising one or more insulating films and one or more layers of conductor electrode patterns, wherein at least one of the insulating films consists of a fluorene skeleton-containing epoxy acrylate resin, and to a method of making a multilayer interconnection structure including the steps of roughening the surface of an insulating resin layer and forming a conductor thereon by electroless plating, wherein the average roughness (Ra), maximum roughness (Ry) and conductor thickness (T) of the roughened surface of the insulating resin layer satisfy the following relations: 0.2.ltoreq.Ra.ltoreq.0.6 (unit: .mu.m) (1) 0.02.ltoreq.Ra/T.ltoreq.0.2 (2) 0.05.ltoreq.Ry/T.ltoreq.0.5 (3) and catalyst nuclei for electroless plating are supplied by applying a solution of a metallic salt to the roughened surface of the insulating resin layer or dipping the substrate in a solution of a metallic salt, drying and heat-treating the substrate, and then subjecting it to displacement palladium plating.
摘要翻译：本发明涉及一种互连结构，其包括一个或多个绝缘膜和一层或多层导体电极图案，其中绝缘膜中的至少一层由含芴骨架的环氧丙烯酸酯树脂组成，以及制备多层互连结构，包括通过无电解电镀使绝缘树脂层的表面粗糙化并在其上形成导体的步骤，其中绝缘树脂的粗糙表面的平均粗糙度（Ra），最大粗糙度（Ry）和导体厚度（T）层满足以下关系：0.2

7. 发明授权

US4724283A Multi-layer circuit board having a large heat dissipation 失效
标题翻译：散热大的多层电路板
公开(公告)号：US4724283A
公开(公告)日：1988-02-09
申请号：US912537
申请日：1986-09-29
申请人： Yuzo Shimada , Yasuhiro Kurokawa , Kazuaki Utsumi
发明人： Yuzo Shimada , Yasuhiro Kurokawa , Kazuaki Utsumi
IPC分类号： H05K3/46 , H01L23/15 , H01L23/538 , H05K1/03 , H05K1/09 , H05K1/00
CPC分类号： H01L23/5383 , H01L23/15 , H01L2924/0002 , H05K1/092 , H05K3/4611 , H05K3/4629
摘要： A multi-layer circuit board is disclosed which includes a plurality of AlN ceramic layers stocked and combined as an integrated form and wiring layers interposed at different levels between the AlN ceramic layers. The wiring layers are made of a mixture of tungsten and AlN ceramic particles, the content of the AlN ceramic particles being 0.5 to 2.0 wt. %. A plurality of through-holes are formed in the AlN ceramic layers to interconnect the wiring layers formed at different levels.
摘要翻译：公开了一种多层电路板，其包括存储并组合为集成形式的多个AlN陶瓷层和插入在AlN陶瓷层之间的不同层次的布线层。布线层由钨和AlN陶瓷颗粒的混合物制成，AlN陶瓷颗粒的含量为0.5-2.0wt。％。在AlN陶瓷层中形成多个通孔以使形成在不同层次的布线层互相连接。

8. 发明授权

US4574255A MMC Substrate including capacitors having perovskite structure dielectric and electrical devices including MMC substrate 失效
标题翻译： MMC衬底包括具有钙钛矿结构电介质的电容器和包括MMC衬底的电气器件
公开(公告)号：US4574255A
公开(公告)日：1986-03-04
申请号：US561506
申请日：1983-12-15
申请人： Shuzo Fujii , Yuzo Shimada , Kazuaki Utsumi , Yutaka Saito
发明人： Shuzo Fujii , Yuzo Shimada , Kazuaki Utsumi , Yutaka Saito
IPC分类号： C04B35/497 , C04B35/499 , G01K7/32 , H01L23/15 , H01L27/01 , H03B5/36 , H05K1/03 , H05K1/09 , H05K1/16 , H05K3/46 , H03L7/06 , H03L1/02
CPC分类号： C04B35/499 , C04B35/497 , G01K7/32 , H01L23/15 , H01L27/01 , H03B5/36 , H05K1/162 , H01L2924/0002 , H01L2924/3011 , H05K1/0306 , H05K1/092 , H05K1/167 , H05K3/4614 , H05K3/4629 , H05K3/4688 , Y10S331/03
摘要： Between insulative layers (31-37, 41-44), a multilayer substrate comprises at least one dielectric layer (26-29). It is possible to form capacitors (58), resistors (46), and wiring conductors (61, 62) in the substrate. The at least one dielectric layer should be of at least one dielectric composition which has a perovskite structure. Preferably, each insulative layer is of an insulating material which consists essentially of aluminum oxide and lead borosilicate glass. The substrate is convenient in manufacturing a crystal oscillator by mounting a crystal vibrator (71) and a transistor (72) on the principal surface(s). Examples of the dielectric composition are:Pb[(Fe.sub.2/3.W.sub.1/3).sub.0.33 (Fe.sub.1/2.Nb.sub.1/2).sub.0.67 ]O.sub.3,Pb[(Mn.sub.1/3.Nb.sub.2/3).sub.0.01 (Mg.sub.1/2.W.sub.1/2).sub.0.30 (Ni.sub.1/3.Nb.sub.2/3).sub.0.49 Ti.sub.0.20 ]O.sub.3,andPb[(Mg.sub.1/2.W.sub.1/2).sub.0.66 Ti.sub.0.34 ]O.sub.3.
摘要翻译：在绝缘层（31-37,41-44）之间，多层衬底包括至少一个电介质层（26-29）。可以在基板中形成电容器（58），电阻器（46）和布线导体（61,62）。所述至少一个电介质层应为具有钙钛矿结构的至少一种介电组合物。优选地，每个绝缘层是由氧化铝和硼硅酸铅玻璃基本上组成的绝缘材料。通过将晶体振子（71）和晶体管（72）安装在主面上，该衬底便于制造晶体振荡器。电介质组成的例子有：Pb [（Fe2 / 3.W1 / 3）0.33（Fe1 / 2.Nb1 / 2）0.67] O3，Pb [（Mn1 / 3.Nb2 / 3）0.01（Mg1 / 2.W1 /2)0.30(Ni1/3.Nb2/3)0.49Ti0.20]03，Pb [（Mg1 / 2.W1 / 2）0.66Ti0.34] O3。

9. 发明授权

US4567542A Multilayer ceramic substrate with interlayered capacitor 失效
标题翻译：带层间电容器的多层陶瓷基板
公开(公告)号：US4567542A
公开(公告)日：1986-01-28
申请号：US603109
申请日：1984-04-23
申请人： Yuzo Shimada , Kazuaki Utsumi , Teruyuki Ikeda , Masanori Suzuki
发明人： Yuzo Shimada , Kazuaki Utsumi , Teruyuki Ikeda , Masanori Suzuki
IPC分类号： H05K1/03 , H05K1/09 , H05K1/16 , H05K3/46 , H01G4/10
CPC分类号： H05K3/4611 , H05K1/162 , H05K3/4629 , H05K1/0306 , H05K1/092 , H05K3/4688
摘要： A multilayer ceramic substrate with an interlayered capacitor has a large electrostatic capacity and a high flexural strength, such as 1,500 Kg/cm.sup.2 or more, and yet is manufactured at a relatively low firing or sintering temperature. A first ceramic body includes a plurality of laminated first ceramic sheets with a high dielectric constant and with a plurality of internal electrodes sandwiching the respective first ceramic sheets to form capacitors therebetween. A second ceramic body is laminated over one side of the first ceramic body and has a plurality of laminated second ceramic sheets with a low dielectric constant. A plurality of first wiring layers are sandwiched between the second ceramic sheets. A third ceramic body is laminated over the other side of the first ceramic body and has a plurality of laminated third ceramic sheets formed of the same ceramic material that is used to make the second ceramic sheets. The second and third ceramic bodies are thicker than the first ceramic body. A second embodiment of the invention is a hybrid ceramic structure made of glass-ceramic insulator layers sandwiching at least one dielectric layer with interposed circuit patterns formed thereon.
摘要翻译：具有层间电容器的多层陶瓷基板具有大的静电容量和高弯曲强度，例如1500Kg / cm 2以上，并且在相对低的烧制或烧结温度下制造。第一陶瓷体包括具有高介电常数的多个叠层的第一陶瓷片和多个内部电极，夹着各自的第一陶瓷片以在它们之间形成电容器。第二陶瓷体层压在第一陶瓷体的一侧上，并且具有多个具有低介电常数的叠层的第二陶瓷片。多个第一布线层被夹在第二陶瓷片之间。第三陶瓷体层叠在第一陶瓷体的另一侧上，并且具有由用于制造第二陶瓷片的相同陶瓷材料形成的多个叠层的第三陶瓷片。第二陶瓷体和第三陶瓷体比第一陶瓷体厚。本发明的第二实施例是由玻璃 - 陶瓷绝缘体层制成的混合陶瓷结构，其夹持形成在其上的插入的电路图案的至少一个电介质层。

10. 发明授权

US4536435A Multilayer substrate including layers of an alumina and borosilicate-lead-glass ceramic material 失效
标题翻译：包括氧化铝和硼硅酸盐 - 铅 - 玻璃陶瓷材料层的多层衬底
公开(公告)号：US4536435A
公开(公告)日：1985-08-20
申请号：US434238
申请日：1982-10-14
申请人： Kazuaki Utsumi , Yuzo Shimada , Masanori Suzuki , Hideo Takamizawa
发明人： Kazuaki Utsumi , Yuzo Shimada , Masanori Suzuki , Hideo Takamizawa
IPC分类号： H05K3/28 , B32B9/00 , B32B15/04 , B32B18/00 , C03C10/00 , H01B3/12 , H01L23/15 , H05K1/00 , H05K1/03 , H05K3/46 , B32B3/00
CPC分类号： H01L23/15 , C03C10/0054 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/4629 , H05K3/4676 , Y10S428/901 , Y10T428/24917 , Y10T428/24926
摘要： A multilayer glass-ceramic substrate comprises insulator layers of a composition consisting essentially of, when components are expressed as oxides in percent by weight, 40-60 percent of aluminum oxide, 1-40 percent of lead oxide, 1-30 percent of boron oxide, 2-40 percent of silicon dioxide, 0.01-25 percent of at least one oxide of chemical element(s) of Group II of the periodic table, and 0.01-10 percent of at least one oxide of Group IV element(s) except carbon, silicon, and lead. Each insulator layer may be only from 190 microns down to 10 microns thick. The substrate has a flexural strength of 2,100 kg/cm.sup.2 or more. Preferably, the Group II element(s) is magnesium, calcium, strontium, barium, and/or zinc. The Group IV element(s) is zirconium, titanium, germanium, and/or tin. When the percentages are 40-60 for aluminum oxide, 4.1-16.6 for lead oxide, 1.0-10.0 for boron oxide, 14.0-39.1 for silicon dioxide, 0.1-4.8 for magnesium oxide, 2.0-10.0 for calcium oxide, 0.05-3.0 for barium oxide, 0.01-3.0 for zirconium oxide, and 0.01-2.5 for titanium oxide, the substrate has a flexural strength of 3,000 kg/cm.sup.2 or more and an interlayer leakage current of 8 microamperes or less. Each insulator layer has a structure of a vitreous network of borosilicate-lead series glass with the interstices occupied by crystals of aluminum oxide and microcrystalline structures which are obtained by reaction of aluminum oxide and glass of the borosilicate lead series.
摘要翻译：多层玻璃陶瓷基板包括绝缘体层，其组成基本上由组分按百分比表示为氧化物，40-60％的氧化铝，1-40％的氧化铅，1-30％的氧化硼，2-40％的二氧化硅，0.01-25％的至少一种元素周期表第II族化学元素的氧化物和0.01-10％的至少一种IV族元素的氧化物，除了碳，硅和铅。每个绝缘体层可以仅为190微米至10微米厚。基材的弯曲强度为2100公斤/厘米2以上。优选地，II族元素是镁，钙，锶，钡和/或锌。 IV族元素是锆，钛，锗和/或锡。当氧化铝的百分比为40-60，氧化铅为4.1-16.6，氧化硼为1.0-10.0，二氧化硅为14.0-39.1，氧化镁为0.1-4.8，氧化钙为2.0-10.0，氧化钙为0.05〜3.0 氧化钡，氧化锆为0.01-3.0，氧化钛为0.01〜2.5，基板的挠曲强度为3000kg / cm 2以上，层间漏电流为8微安以上。每个绝缘体层具有硼硅酸盐 - 铅系列玻璃的玻璃质网络的结构，其中通过氧化铝和硼硅酸铅系列的玻璃的反应获得氧化铝晶体和微晶结构所占据的空隙。

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