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1. 发明授权

US07495669B2 Image processing apparatus and image processing method 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US07495669B2
公开(公告)日：2009-02-24
申请号：US10739344
申请日：2003-12-19
申请人： Katsutoshi Ushida , Yuichi Naoi , Yoshiaki Katahira , Yasuyuki Nakamura , Koichi Morishita , Makoto Fukuo
发明人： Katsutoshi Ushida , Yuichi Naoi , Yoshiaki Katahira , Yasuyuki Nakamura , Koichi Morishita , Makoto Fukuo
IPC分类号： G06F13/00 , G06F15/167 , G06F12/02
CPC分类号： G06T1/60 , G06T1/0007
摘要： To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.
摘要翻译：为了提供与CCD和CIS兼容的图像处理技术，其控制存储器中的每个设备读取的图像数据的存储器以及用于每个矩形区域的存储的数据的读取以获得高的存储器效率，图像处理装置存储区域控制部分，对于在第一存储器上位映射的图像数据，设置在主扫描方向和副扫描方向上分割的矩形区域，生成地址信息以读出对应于矩形的图像数据的地址信息区域，与设置的矩形区域对应的存储器控制部分，读出对应于矩形区域的图像数据的存储器控制部分，并且根据生成的地址信息将图像数据DMA传送到第二存储器;以及图像处理部件，其执行通过使用第二存储器对DMA传送数据的每个矩形区域进行图像处理。

2. 发明授权

US07675523B2 Image processing apparatus and image processing method 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US07675523B2
公开(公告)日：2010-03-09
申请号：US11487370
申请日：2006-07-17
申请人： Katsutoshi Ushida , Yuichi Naoi , Yoshiaki Katahira , Yasuyuki Nakamura , Koichi Morishita , Makoto Fukuo
发明人： Katsutoshi Ushida , Yuichi Naoi , Yoshiaki Katahira , Yasuyuki Nakamura , Koichi Morishita , Makoto Fukuo
IPC分类号： G06F13/00 , G06F15/167 , G06F12/06
CPC分类号： G06T1/60 , G06T1/0007
摘要： To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.
摘要翻译：为了提供与CCD和CIS兼容的图像处理技术，其控制存储器中的每个设备读取的图像数据的存储器以及用于每个矩形区域的存储的数据的读取以获得高的存储器效率，图像处理装置存储区域控制部分，对于在第一存储器上位映射的图像数据，设置在主扫描方向和副扫描方向上分割的矩形区域，生成地址信息以读出对应于矩形的图像数据的地址信息区域，与设置的矩形区域对应的存储器控制部分，读出对应于矩形区域的图像数据的存储器控制部分，并且根据生成的地址信息将图像数据DMA传送到第二存储器;以及图像处理部件，其执行通过使用第二存储器对DMA传送数据的每个矩形区域进行图像处理。

3. 发明申请

US20060256120A1 Image processing apparatus and image processing method 有权
公开(公告)号：US20060256120A1
公开(公告)日：2006-11-16
申请号：US11487370
申请日：2006-07-17
申请人： Katsutoshi Ushida , Yuichi Naoi , Yoshiaki Katahira , Yasuyuki Nakamura , Koichi Morishita , Makoto Fukuo
发明人： Katsutoshi Ushida , Yuichi Naoi , Yoshiaki Katahira , Yasuyuki Nakamura , Koichi Morishita , Makoto Fukuo
IPC分类号： G09G5/39
CPC分类号： G06T1/60 , G06T1/0007
摘要： To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.

4. 发明授权

US07817297B2 Image processing apparatus and image processing method 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US07817297B2
公开(公告)日：2010-10-19
申请号：US10739345
申请日：2003-12-19
申请人： Katsutoshi Ushida , Yuichi Naoi , Yoshiaki Katahira , Koichi Morishita
发明人： Katsutoshi Ushida , Yuichi Naoi , Yoshiaki Katahira , Koichi Morishita
IPC分类号： G06K15/00 , H04N1/405 , H04N1/04 , G06F12/00 , G06K9/54
CPC分类号： H04N1/191 , H04N2201/212
摘要： To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes an input section which executes input processing of image data read by an image reading device in accordance with the data output format of the device, an output data control section which distributes the image data that has undergone the input processing by the input section in accordance with the output format of the image reading device, an address generation section which generates address information corresponding to the output format to store the distributed image data in a memory, and a memory control section which DMA-transfers the distributed image data to the memory and stores the image data on the basis of the generated address information.
摘要翻译：为了提供与CCD和CIS兼容的图像处理技术，其控制存储器中的每个设备读取的图像数据的存储器以及用于每个矩形区域的存储的数据的读取以获得高的存储器效率，图像处理装置包括输入部，其根据设备的数据输出格式执行由图像读取装置读取的图像数据的输入处理;输出数据控制部，其根据输入部分分配已经经过输入处理的图像数据利用图像读取装置的输出格式，生成对应于输出格式的地址信息以将分布式图像数据存储在存储器中的地址生成部分，以及将分布式图像数据DMA传送到存储器的存储器控制部分，以及基于生成的地址信息来存储图像数据。

5. 发明授权

US08320022B2 Image forming apparatus and image forming method 有权
公开(公告)号：US08320022B2
公开(公告)日：2012-11-27
申请号：US13458340
申请日：2012-04-27
申请人： Koichi Morishita , Hisashi Ishikawa
发明人： Koichi Morishita , Hisashi Ishikawa
IPC分类号： G06K15/00 , G06K15/02 , H04N1/60 , B41J29/38
CPC分类号： H04N1/407 , G06K15/107 , H04N1/00002 , H04N1/00015 , H04N1/00023 , H04N1/00034 , H04N1/00047 , H04N1/0005 , H04N1/00055 , H04N1/00063 , H04N1/00082 , H04N1/2307 , H04N1/2346
摘要： An image forming apparatus which forms a halftone image on a print medium (200) using multipass processing of scanning a single area on the print medium (200) by a printhead (220) N times and forming dots every scan operation includes a pass division table (410) used to set the print density ratio of each scan operation, a print data generation unit (370) which generates print data of each scan operation, a printer engine (180) which prints a halftone image on the print medium (200) on the basis of the generated print data, and a sensor (340) which detects the state of printing on the print medium (200) by the printer engine (180). The print data generation unit (370) corrects print data in synchronism with printing by the printer engine (180) on the basis of the set print density ratio and the detected printing state.

6. 发明申请

US20110161715A1 INFORMATION PROCESSING APPARATUS OR INFORMATION PROCESSING METHOD 有权
标题翻译：信息处理装置或信息处理方法
公开(公告)号：US20110161715A1
公开(公告)日：2011-06-30
申请号：US12971684
申请日：2010-12-17
申请人： Akiyoshi Momoi , Koichi Morishita
发明人： Akiyoshi Momoi , Koichi Morishita
IPC分类号： G06F1/12
CPC分类号： H03K19/00323 , H03L7/07 , H03L7/0805 , H03L7/0812
摘要： According to the present invention, a phase shift of data received by an external device controller is delayed and corrected, and a control signal used for the data load control on the external device controller side is delayed period-by-period. Further, the phase shift is adjusted and then the control signal is adjusted. The adjustment can beneficially be performed very quickly. Moreover, the present invention is also beneficial for preventing a failure to load data.
摘要翻译：根据本发明，延迟和校正由外部设备控制器接收的数据的相移，并且用于外部设备控制器侧的数据负载控制的控制信号被逐周期地延迟。此外，调整相移，然后调整控制信号。调整可以很有效地执行。此外，本发明对于防止数据加载失败也是有益的。

7. 发明申请

US20100223409A1 BUS ARBITRATION APPARATUS AND METHOD 有权
标题翻译：总线仲裁装置和方法
公开(公告)号：US20100223409A1
公开(公告)日：2010-09-02
申请号：US12095599
申请日：2007-06-12
申请人： Toshiaki Minami , Shunichi Kaizu , Yasunari Nagamatsu , Daisuke Shiraishi , Makoto Fujiwara , Koji Moriya , Koichi Morishita
发明人： Toshiaki Minami , Shunichi Kaizu , Yasunari Nagamatsu , Daisuke Shiraishi , Makoto Fujiwara , Koji Moriya , Koichi Morishita
IPC分类号： G06F13/362 , G06F13/00
CPC分类号： G06F13/362
摘要： A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.
摘要翻译：根据本发明的总线仲裁装置适当地仲裁多个主机和多个从机之间的总线使用权，以便有效地执行所请求的数据传送。仲裁器A 5接收由主设备A 1和B 2生成的从设备A 3的数据传送请求。仲裁器A 5与仲裁器B 4协同工作，并且仲裁关于从设备A的数据传送请求的争用 3由主人A 1和B 2生成。

8. 发明授权

US08909970B2 Information processing apparatus or information processing method which supplies a clock to an external device 有权
标题翻译：向外部设备提供时钟的信息处理装置或信息处理方法
公开(公告)号：US08909970B2
公开(公告)日：2014-12-09
申请号：US13518344
申请日：2010-12-21
申请人： Akiyoshi Momoi , Koichi Morishita
发明人： Akiyoshi Momoi , Koichi Morishita
IPC分类号： H04L7/00 , H04L7/10 , H04L7/033
CPC分类号： H04L7/10 , H04L7/0337
摘要： If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information processing apparatus may require an additional process for adjusting a data latch timing.Delay information indicating a relationship between a calibration pattern to be received and an amount of cycle delay is stored in advance. Thus, the time required for detecting an amount of cycle delay, which is equivalent to the amount by which a signal for controlling a data latch mechanism in the information processing apparatus to stop its operation is delayed, can be reduced.
摘要翻译：如果信息处理设备从外部设备接收到的数据相对于信息处理设备的时钟被延迟一个周期以上，则信息处理设备可能需要用于调整数据锁存定时的附加处理。预先存储指示要接收的校准模式与循环延迟量之间的关系的延迟信息。因此，可以减少用于检测循环延迟量所需的时间，其等于用于控制信息处理装置中的数据锁存机构的信号停止其操作的量被延迟的量。

9. 发明申请

US20120259438A1 INFORMATION PROCESSING APPARATUS OR INFORMATION PROCESSING METHOD 有权
标题翻译：信息处理装置或信息处理方法
公开(公告)号：US20120259438A1
公开(公告)日：2012-10-11
申请号：US13518321
申请日：2010-12-21
申请人： Akiyoshi Momoi , Koichi Morishita
发明人： Akiyoshi Momoi , Koichi Morishita
IPC分类号： G05B19/00
CPC分类号： H04L7/0091 , G05B19/00 , H04L7/0008 , H04L7/0037 , H04L7/10
摘要： If data received by an external device controller from an external device is delayed by one cycle or more with respect to an output clock of the external device controller, a delay may not necessarily be detected with an existing configuration.When a data latch timing of the external device controller is adjusted, gating of or releasing gating of an output clock of the external device controller is performed in accordance with predetermined gating information, thus improving the accuracy of calibration for adjusting the data latch timing.
摘要翻译：如果外部设备控制器从外部设备接收到的数据相对于外部设备控制器的输出时钟延迟了一个周期或更长时间，则可能不一定会用现有配置来检测延迟。当调整外部设备控制器的数据锁定定时时，根据预定的门控信息执行外部设备控制器的输出时钟门控或释放门控，从而提高了调整数据锁存定时的校准精度。

10. 发明申请

US20110219156A1 BUS ARBITRATION APPARATUS AND METHOD 有权
标题翻译：总线仲裁装置和方法
公开(公告)号：US20110219156A1
公开(公告)日：2011-09-08
申请号：US13112938
申请日：2011-05-20
申请人： Toshiaki Minami , Shunichi Kaizu , Yasunari Nagamatsu , Daisuke Shiraishi , Makoto Fujiwara , Koji Moriya , Koichi Morishita
发明人： Toshiaki Minami , Shunichi Kaizu , Yasunari Nagamatsu , Daisuke Shiraishi , Makoto Fujiwara , Koji Moriya , Koichi Morishita
IPC分类号： G06F13/14
CPC分类号： G06F13/362
摘要： A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.
摘要翻译：根据本发明的总线仲裁装置适当地仲裁多个主机和多个从机之间的总线使用权，以便有效地执行所请求的数据传送。仲裁器A 5接收由主设备A 1和B 2生成的从设备A 3的数据传送请求。仲裁器A 5与仲裁器B 4协同工作，并且仲裁关于从设备A的数据传送请求的争用 3由主人A 1和B 2生成。

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