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1. 发明授权

US6032221A Flash memory embedded microcomputer 失效
标题翻译：闪存嵌入式微机
公开(公告)号：US6032221A
公开(公告)日：2000-02-29
申请号：US19040
申请日：1998-02-05
申请人： Katsunobu Hongo
发明人： Katsunobu Hongo
IPC分类号： G11C16/06 , G06F15/78 , G11C16/34 , G11C29/48 , G11C29/50
CPC分类号： G11C16/34 , G11C29/48 , G11C29/50 , G11C16/04 , G11C2029/5004
摘要： A flash memory capable of solving a problem of a conventional flash memory in that it requires considerable time and effort to measure supply voltages generated in the flash memory during writing, erasing and verifying operations, and is difficult to acquire accurate results, because they cannot be measured by a tester and must be measured manually by putting a probe directly to voltage supply lines. The present flash memory includes a first voltage transfer circuit for supplying an A/D converter with an analog signal input to a microcomputer, and a second voltage transfer circuit for supplying the input terminal of the A/D converter with a programming voltage generated by a flash memory voltage generator, and brings the first voltage transfer circuit into a conducting state and the second voltage transfer circuit into a nonconducting state in a normal operation mode, and brings the first voltage transfer circuit into the nonconducting state and the second voltage transfer circuit into the conducting state in a voltage measurement mode to measure voltages on the flash memory power supply lines.
摘要翻译：一种能够解决常规闪速存储器问题的闪速存储器，因为在写入，擦除和验证操作期间测量闪存中产生的电源电压需要相当多的时间和精力，并且难以获得准确的结果，因为它们不能由测试仪测量，必须通过将探头直接放置在电源线上进行手动测量。本闪速存储器包括用于向A / D转换器提供输入到微型计算机的模拟信号的第一电压传输电路和用于向A / D转换器的输入端提供由闪存电压发生器，并且使第一电压传输电路进入导通状态，并将第二电压传输电路以正常操作模式进入非导通状态，并且使第一电压传输电路进入非导通状态，并将第二电压传输电路转换为电压测量模式中的导通状态来测量闪存电源线上的电压。

2. 发明授权

US4914428A Digital remote control transmission apparatus 失效
标题翻译：数字遥控传输装置
公开(公告)号：US4914428A
公开(公告)日：1990-04-03
申请号：US55129
申请日：1987-05-28
申请人： Hiroshi Kobayashi , Shinji Suda , Katsunobu Hongo , Daisuke Shichinohe , Masako Hiroma
发明人： Hiroshi Kobayashi , Shinji Suda , Katsunobu Hongo , Daisuke Shichinohe , Masako Hiroma
IPC分类号： G08C19/28
CPC分类号： G08C19/28
摘要： A digital remote control apparatus for transmitting digital instruction signals to a controllable apparatus includes a transmitter for transmitting a coded digital instruction signal composed of a sequence of synchronization pulses having a predetermined period and data pulses each inserted between successive synchronization pulses at predetermined positions therein dependent upon whether the data pulses represents a "0" bit or a "1" bit. The receiving apparatus distinguishes between "0" and "1" bits by detecting the length of an interval between the leading edge of a synchronization pulse and the leading edge of an adjacent data pulse and determines the existence of noise if more than one data pulse is detected between successive synchronzation pulses. In this way, information decoding is facilitated by enabling the length of each data word to be constant, regardless of the number of ones and zeroes in the word, and also facilitates the detection of communication transmission error by detecting the presence of more than one data pulse between successive synchronization pulses of a constant period as being noise.
摘要翻译：一种用于将数字指令信号发送到可控制装置的数字遥控装置包括发射机，用于发送编码的数字指令信号，该编码数字指令信号由具有预定周期的同步脉冲序列组成，数据脉冲各自插入在依赖于数据脉冲是否表示“0”位或“1”位。接收装置通过检测同步脉冲的前沿与相邻数据脉冲的前沿之间的间隔的长度来区分“0”和“1”比特，并且如果多于一个的数据脉冲是在连续的同步脉冲之间检测。以这种方式，通过使得每个数据字的长度能够保持恒定，而不管单词中的一个和多个的数目如何，便于信息解码，并且还通过检测多于一个数据的存在而有助于检测通信传输错误在一个恒定周期的连续同步脉冲之间的脉冲作为噪声。

3. 发明授权

US5983330A Microcomputer with watchdog timer settings suppressing interrupt request processing over memory data write operation to flash memory 失效
标题翻译：具有看门狗定时器设置的微电脑抑制中断请求处理超过存储器数据写入操作到闪存
公开(公告)号：US5983330A
公开(公告)日：1999-11-09
申请号：US917189
申请日：1997-08-25
申请人： Yuichiro Miwa , Katsunobu Hongo
发明人： Yuichiro Miwa , Katsunobu Hongo
IPC分类号： G06F11/30 , G06F11/00 , G06F12/08
CPC分类号： G06F11/0757
摘要： A microcomputer capable of solving a problem in that the load of software is heavy for setting a watchdog timer in a conventional microcomputer. It includes a switching circuit which supplies a central processing unit with the output of the watchdog timer as an interrupt signal unless a memory data write mode for writing data to a memory is not designated from the outside of the microcomputer, and which inhibits an overflow signal of the watchdog timer from being supplied to the central processing unit when the memory data write mode is designated from the outside of the microcomputer.
摘要翻译：微型计算机能够解决在现有微型计算机中设置看门狗定时器的软件负担很重的问题。它包括切换电路，其将中央处理单元与看门狗定时器的输出提供为中断信号，除非从微型计算机的外部指定用于将数据写入存储器的存储器数据写入模式，并且禁止溢出信号当从微型计算机的外部指定存储器数据写入模式时，看门狗定时器被提供给中央处理单元。

4. 发明授权

US5826059A Microcomputer for emulation 失效
标题翻译：微电脑仿真
公开(公告)号：US5826059A
公开(公告)日：1998-10-20
申请号：US574142
申请日：1995-12-18
申请人： Daijiro Harada , Katsunobu Hongo , Masato Koura
发明人： Daijiro Harada , Katsunobu Hongo , Masato Koura
IPC分类号： G06F11/22 , G06F11/36 , G06F12/06 , G06F15/78 , G06F9/455
CPC分类号： G06F11/3652 , G06F12/0646
摘要： A microcomputer for emulation which has been conventionally unusable when built-in RAM capacities are different, because an access to an internal function circuit is different in bus control, wait condition and the like from the access to an external memory area, and despite the above fact, which now becomes usable by including a built-in RAM 17, a higher address decoder (virtual RAM address decoder) for generating a virtual RAM address space corresponding to a plurality of virtual RAM capacities within a range in which installed capacity of the built-in RAM 17 is made a maximum value, and a RAM capacity selection flag 36 for specifying any one of a plurality of virtual RAM address spaces which can be generated by the higher address decoder 22.
摘要翻译：在内置RAM容量不同的情况下，由于对内部功能电路的访问在总线控制，等待条件等的访问方面与外部存储区域的访问不同，所以通常不能使用的仿真微型计算机，尽管如此事实上，现在可以通过包括内置RAM 17，更高地址解码器（虚拟RAM地址解码器）来生成与多个虚拟RAM容量相对应的虚拟RAM地址空间可用的范围，该范围内的内置RAM - 将RAM17设为最大值，以及RAM容量选择标志36，用于指定可由高地址解码器22产生的多个虚拟RAM地址空间中的任一个。

5. 发明授权

US5734878A Microcomputer in which a CPU is operated on the basis of a clock signal input into one of two clock terminals 失效
标题翻译：基于输入到两个时钟端子之一的时钟信号来操作CPU的微计算机
公开(公告)号：US5734878A
公开(公告)日：1998-03-31
申请号：US546126
申请日：1995-10-20
申请人： Katsunobu Hongo
发明人： Katsunobu Hongo
IPC分类号： G06F15/78 , G06F1/06 , G06F1/08 , H01L21/82 , H01L21/822 , H01L27/04 , G06F1/04
CPC分类号： G06F1/08
摘要： A microcomputer constituted so that an oscillation state selection signal indicative of whether a clock inputted to a first clock terminal is a clock generated at a clock generating circuit is given to a first gate circuit interposed between a first clock terminal and a second clock terminal, and a first gate circuit is placed in the transmissible state when an oscillation state selection signal is on a first state while a first gate circuit is placed in a state not to be able to transmit a signal when the oscillation state selection signal is on a second state.
摘要翻译：微型计算机被构造成使得表示输入到第一时钟端子的时钟是否是在时钟发生电路产生的时钟的振荡状态选择信号被提供给插在第一时钟端子和第二时钟端子之间的第一门电路，以及当振荡状态选择信号处于第一状态时，第一门电路处于可传播状态，而当振荡状态选择信号处于第二状态时，第一门电路处于不能发送信号的状态。

6. 发明授权

US6127207A Semiconductor integrated circuit and fabrication method therefor 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US6127207A
公开(公告)日：2000-10-03
申请号：US225504
申请日：1999-01-06
申请人： Katsunobu Hongo
发明人： Katsunobu Hongo
IPC分类号： H01L21/82 , H01L23/50 , H01L27/02 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/50 , H01L27/0207 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/48465 , H01L2224/49171 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01079 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor integrated circuit and a fabrication method therefor has the configuration that the number of pad driver cells 21 to 23 are equal to or more than the number of input/output control circuits 11 to 13, poly-silicon wirings 111 to 113 are connected to an input terminal IN and output terminals CP and CN in each of the input/output control circuit 11 to 13 in a wiring region LIN and poly-silicon wirings 211 to 233 are connected to input terminals CP and CN and an output terminal-IN of each of the pad driver cells 21 to 23 in the wiring region, and the poly-silicon wirings 111 to 133 are connected to poly-silicon wirings 211 to 233 through aluminum wirings.
摘要翻译：半导体集成电路及其制造方法的结构是，焊盘驱动器单元21〜23的数量等于或大于输入/输出控制电路11至13的数量，多晶硅布线111至113连接到在布线区域LIN和多晶硅布线211至233中的每个输入/输出控制电路11至13中的输入端子IN和输出端子CP和CN连接到输入端子CP和CN以及输出端子IN 布线区域中的每个焊盘驱动器单元21至23以及多晶硅布线111至133通过铝布线连接到多晶硅布线211至233。

7. 发明授权

US6111395A Power supply voltage step-down circuitry 失效
标题翻译：电源电压降压电路
公开(公告)号：US6111395A
公开(公告)日：2000-08-29
申请号：US436245
申请日：1999-11-09
申请人： Takuya Hirade , Masato Koura , Katsunobu Hongo
发明人： Takuya Hirade , Masato Koura , Katsunobu Hongo
IPC分类号： G05F1/00 , G05F1/10 , G05F1/46 , G05F1/445
CPC分类号： G05F1/465
摘要： Power supply voltage step-down circuitry comprises a control unit for enabling either a first voltage step-down unit or a second voltage step-down unit according to a control signal applied thereto, a voltage checking unit for checking whether or not the value of a voltage generated by a power supply is equal to or greater than a predetermined value, and for furnishing a checking result signal at a predetermined level when the value of the voltage generated by the power supply is equal to or greater than a predetermined value, and a switching unit for connecting either the power supply or an output of the first step-down unit with a receiver, such as a ROM, according to whether or not the checking result signal from the voltage checking unit is at the predetermined level. The voltage checking unit includes a Schmidt circuit that furnishes the checking result signal at a level corresponding to the value of an output of a checking unit for furnishing the output having a value corresponding to the power supply voltage.
摘要翻译：电源电压降压电路包括：控制单元，用于根据施加的控制信号使第一降压单元或第二降压单元能够实现;电压检查单元，用于检查是否由电源产生的电压等于或大于预定值，并且当由电源产生的电压的值等于或大于预定值时，将检查结果信号提供在预定电平，并且切换单元，用于根据来自电压检查单元的检查结果信号是否处于预定水平，将电源或第一降压单元的输出与诸如ROM的接收器连接。电压检查单元包括施密特电路，其将检查结果信号提供在与检查单元的输出值相对应的电平上，以提供具有与电源电压相对应的值的输出。

8. 发明授权

US5889334A Semiconductor integrated circuit and fabrication method therefor 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US5889334A
公开(公告)日：1999-03-30
申请号：US759882
申请日：1996-12-03
申请人： Katsunobu Hongo
发明人： Katsunobu Hongo
IPC分类号： H01L21/82 , H01L23/50 , H01L27/02 , H01L27/04 , H01L27/118
CPC分类号： H01L23/50 , H01L27/0207 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/48465 , H01L2224/49171 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01079 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor integrated circuit and a fabrication method therefor has the configuration that the number of pad driver cells 21 to 23 are equal to or more than the number of input/output control circuits 11 to 13, poly-silicon wirings 111 to 113 are connected to an input terminal IN and output terminals CP and CN in each of the input/output control circuit 11 to 13 in a wiring region LIN and poly-silicon wirings 211 to 233 are connected to input terminals CP and CN and an output terminal IN of each of the pad driver cells 21 to 23 in the wiring region, and the poly-silicon wirings 111 to 133 are connected to poly-silicon wirings 211 to 233 through aluminum wirings.
摘要翻译：半导体集成电路及其制造方法的结构是，焊盘驱动器单元21〜23的数量等于或大于输入/输出控制电路11至13的数量，多晶硅布线111至113连接到在布线区域LIN和多晶硅布线211至233中的输入/输出控制电路11至13中的每一个中的输入端子IN和输出端子CP和CN连接到输入端子CP和CN以及每个的输出端子IN 的布线区域中的焊盘驱动器单元21至23，并且多晶硅布线111至133通过铝布线连接到多晶硅布线211至233。

9. 发明授权

US5461652A Clock control circuit 失效
标题翻译：时钟控制电路
公开(公告)号：US5461652A
公开(公告)日：1995-10-24
申请号：US387699
申请日：1995-02-13
申请人： Katsunobu Hongo
发明人： Katsunobu Hongo
IPC分类号： G06F1/04 , G04G19/12 , G06F1/06 , G04B47/00 , G04F5/00
CPC分类号： G06F1/08 , G04G19/12 , G06F1/3237 , Y02B60/1221
摘要： A clock control circuit built in a microcomputer, wherein the supply of a system clock to peripherals that are not required to be always operated is suspended in the wait state where the supply of the system clock to a CPU is suspended, thereby decreasing a power to be consumed.
摘要翻译：内置在微计算机中的时钟控制电路，其中向不需要始终操作的外围设备提供系统时钟被暂停在等待状态，其中暂停向CPU供应系统时钟，从而将功率降低到被消耗

10. 发明授权

US5140177A Complementary circuit device returnable to normal operation from latch-up phenomenon 失效
标题翻译：补充电路恢复正常操作的补充电路设备
公开(公告)号：US5140177A
公开(公告)日：1992-08-18
申请号：US442754
申请日：1989-11-29
申请人： Shinji Suda , Hiroshi Kobayashi , Katsunobu Hongo , Hiroyuki Nakao
发明人： Shinji Suda , Hiroshi Kobayashi , Katsunobu Hongo , Hiroyuki Nakao
IPC分类号： H03K17/082 , H03K17/22
CPC分类号： H03K17/223 , H03K17/0822
摘要： A complementary circuit device which cancels a latch-up phenomenon to return to normal operation includes a complementary circuit, a latch-up detection circuit and a reset circuit. The complementary circuit, which is normally started from a prescribed logic state in response to an initial power application of power to the circuit, is susceptible to erroneous restart when the same is resupplied with power immediately after occurrence of a latch-up phenomenon. The latch-up detection circuit detects a latch-up phenomenon occurring in the complementary circuit. The reset circuit resets the complementary circuit to the prescribed logic state in response to an output from the latch-up detection circuit. The complementary circuit is reset again to the prescribed state in a manner similar to the case of initial application of power. The invention facilitates a normal return to operation of a complementary circuit upon cancellation of the latch-up phenomenon.

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