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1. 发明授权

US07405478B2 Substrate package structure and packaging method thereof 有权
标题翻译：基板封装结构及其封装方法
公开(公告)号：US07405478B2
公开(公告)日：2008-07-29
申请号：US11282836
申请日：2005-11-21
申请人： Katsumi Ishikawa , Hiroshi Takei , Nobuya Makino , Tetsuro Yano
发明人： Katsumi Ishikawa , Hiroshi Takei , Nobuya Makino , Tetsuro Yano
IPC分类号： H01L23/42 , H01L23/52
CPC分类号： H01L24/11 , H01L24/81 , H01L2224/10135 , H01L2224/10165 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/14 , H01L2224/17 , H01L2224/81136 , H01L2224/81141 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2224/0401
摘要： A substrate package structure includes bumps disposed on a surface side of a first substrate and a surface side of a second substrate. The bump at the first substrate and the bump at the second substrate are press-fitted to each other while the one surface of the first substrate and the one surface of the second substrate are confronted to each other, thereby connecting the first and second substrates to each other. The bump at the first substrate is constructed so that the tip portion thereof is designed to have a flat surface, and the bump at the second substrate is constructed so that the tip portion is designed to have a projecting portion narrower than the tip portion of the bump at the first substrate.
摘要翻译：衬底封装结构包括设置在第一衬底的表面侧上的凸块和第二衬底的表面侧。第一基板上的凸块和第二基板上的凸起彼此压配合，同时第一基板的一个表面和第二基板的一个表面彼此面对，从而将第一和第二基板连接到彼此。第一基板上的凸起被构造成使得其顶端部分被设计成具有平坦表面，并且第二基板处的凸块被构造成使得末端部分被设计成具有比第一基板的尖端部分窄的突出部分在第一衬底上碰撞。

2. 发明申请

US20060113668A1 Substrate package structure and packaging method thereof 有权
标题翻译：基板封装结构及其封装方法
公开(公告)号：US20060113668A1
公开(公告)日：2006-06-01
申请号：US11282836
申请日：2005-11-21
申请人： Katsumi Ishikawa , Hiroshi Takei , Nobuya Makino , Tetsuro Yano
发明人： Katsumi Ishikawa , Hiroshi Takei , Nobuya Makino , Tetsuro Yano
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/81 , H01L2224/10135 , H01L2224/10165 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/14 , H01L2224/17 , H01L2224/81136 , H01L2224/81141 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2224/0401
摘要： A substrate package structure includes bumps disposed on a surface side of a first substrate and a surface side of a second substrate. The bump at the first substrate and the bump at the second substrate are press-fitted to each other while the one surface of the first substrate and the one surface of the second substrate are confronted to each other, thereby connecting the first and second substrates to each other. The bump at the first substrate is constructed so that the tip portion thereof is designed to have a flat surface, and the bump at the second substrate is constructed so that the tip portion is designed to have a projecting portion narrower than the tip portion of the bump at the first substrate.
摘要翻译：衬底封装结构包括设置在第一衬底的表面侧上的凸块和第二衬底的表面侧。第一基板上的凸块和第二基板上的凸起彼此压配合，同时第一基板的一个表面和第二基板的一个表面彼此面对，从而将第一和第二基板连接到彼此。第一基板上的凸起被构造成使得其顶端部分被设计成具有平坦表面，并且第二基板处的凸块被构造成使得末端部分被设计成具有比第一基板的尖端部分窄的突出部分在第一衬底上碰撞。

3. 发明申请

US20050205995A1 Wire bonding method and semiconductor device 有权
标题翻译：引线接合方法和半导体器件
公开(公告)号：US20050205995A1
公开(公告)日：2005-09-22
申请号：US11063866
申请日：2005-02-24
申请人： Katsumi Ishikawa , Nobuya Makino , Hiroshi Takei
发明人： Katsumi Ishikawa , Nobuya Makino , Hiroshi Takei
IPC分类号： H01L21/60 , B23K31/00 , H01L23/48 , H01L31/0203 , H01R43/02
CPC分类号： B23K20/007 , H01L23/49575 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/48599 , H01L2224/48992 , H01L2224/48997 , H01L2224/4911 , H01L2224/49113 , H01L2224/49427 , H01L2224/78301 , H01L2224/85051 , H01L2224/85181 , H01L2224/85205 , H01L2224/85399 , H01L2224/85951 , H01L2224/85986 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01052 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2224/85186 , H01L2924/00 , H01L2224/48227 , H01L2224/48455 , H01L2924/00015 , H01L2224/4554 , H01L2924/00012
摘要： A wire bonding method for bonding a plurality of conducting wires to connect first conductors and second conductors has the following steps. 1) Bonding a first conducting ball on a first first conductor. 2) Bonding a first conducting wire on the first conducting ball, the first conducting wire being connected to a first second conductor. 3) Bonding a second conducting ball on a second first conductor. 4) Bonding a second conducting wire on the second conducting ball, the second conducting wire being connected to a second second conductor. Here, the second first conductor or the second second conductor is the first conducting wire bonded on the first conducting ball.
摘要翻译：用于接合多根导线以连接第一导体和第二导体的引线接合方法具有以下步骤。 1）将第一导电球接合在第一第一导体上。 2）将第一导线接合在第一导电球上，第一导线连接到第一导体。 3）将第二导电球接合在第二个第一导体上。 4）将第二导线接合在第二导电球上，第二导线连接到第二导体。这里，第二第一导体或第二第二导体是接合在第一导电球上的第一导线。

4. 发明授权

US07285854B2 Wire bonding method and semiconductor device 有权
标题翻译：引线接合方法和半导体器件
公开(公告)号：US07285854B2
公开(公告)日：2007-10-23
申请号：US11063866
申请日：2005-02-24
申请人： Katsumi Ishikawa , Nobuya Makino , Hiroshi Takei
发明人： Katsumi Ishikawa , Nobuya Makino , Hiroshi Takei
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： B23K20/007 , H01L23/49575 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/48599 , H01L2224/48992 , H01L2224/48997 , H01L2224/4911 , H01L2224/49113 , H01L2224/49427 , H01L2224/78301 , H01L2224/85051 , H01L2224/85181 , H01L2224/85205 , H01L2224/85399 , H01L2224/85951 , H01L2224/85986 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01052 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2224/85186 , H01L2924/00 , H01L2224/48227 , H01L2224/48455 , H01L2924/00015 , H01L2224/4554 , H01L2924/00012
摘要： A wire bonding method for bonding a plurality of conducting wires to connect first conductors and second conductors has the following steps. 1) Bonding a first conducting ball on a first first conductor. 2) Bonding a first conducting wire on the first conducting ball, the first conducting wire being connected to a first second conductor. 3) Bonding a second conducting ball on a second first conductor. 4) Bonding a second conducting wire on the second conducting ball, the second conducting wire being connected to a second second conductor. Here, the second first conductor or the second second conductor is the first conducting wire bonded on the first conducting ball.
摘要翻译：用于接合多根导线以连接第一导体和第二导体的引线接合方法具有以下步骤。 1）将第一导电球接合在第一第一导体上。 2）将第一导线接合在第一导电球上，第一导线连接到第一导体。 3）将第二导电球接合在第二个第一导体上。 4）将第二导线接合在第二导电球上，第二导线连接到第二导体。这里，第二第一导体或第二第二导体是接合在第一导电球上的第一导线。

5. 发明授权

US08471622B2 Drive circuit of semiconductor device 失效
标题翻译：半导体器件的驱动电路
公开(公告)号：US08471622B2
公开(公告)日：2013-06-25
申请号：US12760742
申请日：2010-04-15
申请人： Katsumi Ishikawa , Kazutoshi Ogawa , Masahiro Nagasu
发明人： Katsumi Ishikawa , Kazutoshi Ogawa , Masahiro Nagasu
IPC分类号： H03K17/60
CPC分类号： H03K17/08128 , H03K17/127 , H03K17/6877
摘要： The invention provides a switching circuit of a power semiconductor device having connected in parallel SiC diodes with a small recovery current, capable of significantly reducing turn-on loss and recovery loss without increasing the noise in the MHz band, and contributing to reducing the loss and noise of inverters. The present invention provides a switching circuit and an inverter circuit of a power semiconductor device comprising a module combining Si-IGBT and SiC diodes, wherein an on-gate resistance is set smaller than an off-gate resistance.
摘要翻译：本发明提供了一种功率半导体器件的开关电路，其具有并联的SiC二极管，具有小的恢复电流，能够显着降低导通损耗和恢复损耗，而不增加MHz带内的噪声，并有助于减少损耗，逆变器噪声。本发明提供一种功率半导体器件的开关电路和逆变器电路，该功率半导体器件包括组合Si-IGBT和SiC二极管的模块，其中栅极电阻被设定为小于截止栅极电阻。

6. 发明申请

US20130119912A1 Power Conversion Device and Temperature Rise Calculation Method Thereof 有权
标题翻译：电力转换装置及其升温计算方法
公开(公告)号：US20130119912A1
公开(公告)日：2013-05-16
申请号：US13806822
申请日：2011-06-23
申请人： Hideki Ayano , Katsumi Ishikawa , Kazutoshi Ogawa , Tsutomu Kominami , Mami Kunihiro
发明人： Hideki Ayano , Katsumi Ishikawa , Kazutoshi Ogawa , Tsutomu Kominami , Mami Kunihiro
IPC分类号： H02P29/00
CPC分类号： H02P29/0088 , H02M1/32 , H02M7/5387 , H02M2001/327 , H02P21/06 , H02P29/68
摘要： A temperature rise of a semiconductor switching element, which is part of a power conversion device such as an inverter, is estimated by an extremely simple method to assess the degradation and remaining lifetime of the semiconductor switching element.In a heat generation amount calculation unit 12 in a calculation processor 3, current command values Id* and Iq* and voltage command values vu*, vv* and vw* are used to calculate a chip loss. First, current values iu*, iv* and iw* of all output phases are estimated from the current command values. The ON/OFF loss of the chip is represented by a function of an estimated value for a current flowing in each output phase, and the loss can be derived by integration with a PWM carrier frequency f. In addition, with respect to a conduction loss, it is necessary to integrate a conduction time with the estimated current value and a saturation voltage, which is a function of the estimated current value. In this case, the conduction time is calculated from a relationship between a carrier amplitude and the voltage command value in each control cycle fsw of the switching element. In addition, an ambient temperature sensor is added to calculate an absolute temperature.
摘要翻译：作为逆变器等功率转换装置的一部分的半导体开关元件的温度上升通过非常简单的方法来估计半导体开关元件的劣化和剩余寿命来估计。在计算处理器3中的发热量计算单元12中，使用电流指令值Id *和Iq *以及电压指令值vu *，vv *和vw *来计算芯片损耗。首先，从当前命令值估计所有输出相位的当前值iu *，iv *和iw *。芯片的ON / OFF损耗由在每个输出相中流动的电流的估计值的函数表示，并且可以通过与PWM载波频率f的积分来导出损耗。此外，对于导通损耗，需要将导通时间与估计电流值和作为估计电流值的函数的饱和电压进行积分。在这种情况下，根据开关元件的各控制周期fsw中的载波幅度与电压指令值之间的关系来计算导通时间。另外，添加环境温度传感器来计算绝对温度。

7. 发明授权

US07746614B2 Drive circuit for switching device 有权
标题翻译：开关装置的驱动电路
公开(公告)号：US07746614B2
公开(公告)日：2010-06-29
申请号：US12358306
申请日：2009-01-23
申请人： Katsumi Ishikawa , Masataka Sasaki , Koichi Suda
发明人： Katsumi Ishikawa , Masataka Sasaki , Koichi Suda
IPC分类号： H02H3/00 , H02H3/08 , H02H9/02
CPC分类号： H03K17/0828
摘要： A drive circuit that controls a switching device ON/OFF and a soft cutoff command circuit that gradually decreases the gate terminal voltage of the switching device when short circuit of the switching device is detected. Additionally, an ON-pulse retention command circuit retains the output of the drive circuit ON when the gate terminal voltage is judged to have exceeded a specified value by a gate voltage judgment comparator that detects the gate terminal voltage of the switching device.
摘要翻译：控制切换装置ON / OFF的驱动电路和软开关指令电路，当检测到开关装置的短路时，逐渐降低开关装置的栅极端子电压。此外，当通过检测开关装置的栅极端子电压的栅极电压判断比较器判断栅极端子电压已经超过规定值时，ON脉冲保持指令电路保持驱动电路的输出。

8. 发明授权

US07675727B2 Protection circuit for power management semiconductor devices and power converter having the protection circuit 有权
标题翻译：具有保护电路的电源管理半导体器件和电力转换器保护电路
公开(公告)号：US07675727B2
公开(公告)日：2010-03-09
申请号：US11979874
申请日：2007-11-09
申请人： Masataka Sasaki , Katsumi Ishikawa , Ryuichi Saito , Koichi Suda , Katsuaki Takahashi
发明人： Masataka Sasaki , Katsumi Ishikawa , Ryuichi Saito , Koichi Suda , Katsuaki Takahashi
IPC分类号： H02H3/08 , H02H9/02
CPC分类号： B60W20/00 , B60K6/485 , B60L3/003 , B60W10/08 , H02H7/20 , H02M1/32 , H03K17/0828 , H03K17/168 , Y02T10/6226
摘要： A collector voltage of a power management semiconductor device is detected by a first comparator, and when the detected collector voltage exceeds a first reference voltage, the first comparator outputs a first detection signal. Furthermore, a gate voltage of the power management semiconductor device is detected by a second comparator, and when the detected gate voltage exceeds a second reference voltage, the second comparator outputs a second detection signal. The second reference voltage is a minimum gate voltage for feeding a rated power to the power management semiconductor device or over, and less than a line power voltage of a drive circuit of the power management semiconductor device. When both the first detection signal and second detection signal are being outputted, the gate voltage is reduced by a gate voltage reduction means so as to protect the power management semiconductor device from overcurrent and overvoltage.
摘要翻译：功率管理半导体器件的集电极电压由第一比较器检测，并且当检测到的集电极电压超过第一参考电压时，第一比较器输出第一检测信号。此外，由第二比较器检测功率管理半导体器件的栅极电压，并且当检测到的栅极电压超过第二参考电压时，第二比较器输出第二检测信号。第二参考电压是用于向功率管理半导体器件提供额定功率或超过功率管理半导体器件的驱动电路的线电源电压的最小栅极电压。当输出第一检测信号和第二检测信号两者时，通过栅极电压降低装置降低栅极电压，以保护功率管理半导体器件免于过电流和过电压。

9. 发明申请

US20090128974A1 Drive Circuit for Switching Device 有权
标题翻译：开关装置驱动电路
公开(公告)号：US20090128974A1
公开(公告)日：2009-05-21
申请号：US12358306
申请日：2009-01-23
申请人： Katsumi Ishikawa , Masataka Sasaki , Koichi Suda
发明人： Katsumi Ishikawa , Masataka Sasaki , Koichi Suda
IPC分类号： H02H9/02
CPC分类号： H03K17/0828
摘要： A drive circuit that controls a switching device ON/OFF and a soft cutoff command circuit that gradually decreases the gate terminal voltage of the switching device when short circuit of the switching device is detected. Additionally, an ON-pulse retention command circuit retains the output of the drive circuit ON when the gate terminal voltage is judged to have exceeded a specified value by a gate voltage judgment comparator that detects the gate terminal voltage of the switching device.
摘要翻译：控制切换装置ON / OFF的驱动电路和软开关指令电路，当检测到开关装置的短路时，逐渐降低开关装置的栅极端子电压。此外，当通过检测开关装置的栅极端子电压的栅极电压判断比较器判断栅极端子电压已经超过规定值时，ON脉冲保持指令电路保持驱动电路的输出。

10. 发明申请

US20070221994A1 Driver circuit for switching device 失效
标题翻译：开关装置的驱动电路
公开(公告)号：US20070221994A1
公开(公告)日：2007-09-27
申请号：US11657692
申请日：2007-01-25
申请人： Katsumi Ishikawa , Sunao Funakoshi , Kozo Sakamoto , Hidekatsu Onose
发明人： Katsumi Ishikawa , Sunao Funakoshi , Kozo Sakamoto , Hidekatsu Onose
IPC分类号： H01L23/62
CPC分类号： H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal of the switching device with reference to an emitter control terminal or a source control terminal of the switching device, and a unit for detecting a temperature of the switching device. The temperature of the power semiconductor switching device is detected, and a gate drive voltage or a gate drive resistance value is changed based on the detected temperature.
摘要翻译：提供了降低宽间隙半导体器件中的损耗对温度的依赖性的驱动电路。用于电压驱动的功率半导体开关器件的栅极驱动器电路包括功率半导体开关器件，驱动器电路，用于参照开关器件的发射极控制端子或源极控制端子向开关器件的栅极端子提供驱动信号，以及用于检测开关装置的温度的单元。检测功率半导体开关器件的温度，并且基于检测到的温度改变栅极驱动电压或栅极驱动电阻值。

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