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1. 发明授权

US06433287B1 Connection structure 失效
标题翻译：连接结构
公开(公告)号：US06433287B1
公开(公告)日：2002-08-13
申请号：US09612462
申请日：2000-07-07
申请人： Katsuhito Sasaki , Isao Kimura , Mamoru Ishikiriyama
发明人： Katsuhito Sasaki , Isao Kimura , Mamoru Ishikiriyama
IPC分类号： H01R909
CPC分类号： H01L23/528 , H01L23/5226 , H01L2924/0002 , Y10T29/49165 , H01L2924/00
摘要： There is provided a connection structure in which concentration of current in a connection portion of wirings, or of an element and a wiring is prevented. Three slits are formed in each of a first wiring and a second wiring, which extends in a direction perpendicular to a direction in which the first wiring extends, so that distances from the side of a cross internal angle gradually become longer. A portion of a current path is changed by these slits so as to limit current which can flow through the cross internal angle.
摘要翻译：提供了一种连接结构，其中防止了布线的连接部分或元件和布线的电流集中。在与第一布线延伸的方向垂直的方向上延伸的第一布线和第二布线中的每一个中形成有三个狭缝，使得从交叉内角的一侧的距离逐渐变长。通过这些狭缝改变电流路径的一部分，以限制可以流过十字内角的电流。

2. 发明授权

US06424014B1 Semiconductor element with electric field reducing device mounted therein for increasing dielectric strength 有权
公开(公告)号：US06424014B1
公开(公告)日：2002-07-23
申请号：US09734741
申请日：2000-12-13
申请人： Katsuhito Sasaki , Isao Kimura , Mamoru Ishikiriyama
发明人： Katsuhito Sasaki , Isao Kimura , Mamoru Ishikiriyama
IPC分类号： H01L2976
摘要： Expansion promotion means (24) for more efficiently promoting the expansion of the depletion layer (19) than the electrically insulating film(14) having a suppressor electrode layer (20) buried therein is arranged between narrow portions (23b) of the suppressor electrode layer to control the expansion of the depletion layer (19), by which arrangement the spacing s between the narrow portions (23b) can be reduced without decreasing the field reducing effect of the field reduction means, which contains the suppressor electrode layer.

3. 发明授权

US06452245B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06452245B1
公开(公告)日：2002-09-17
申请号：US09635576
申请日：2000-08-09
申请人： Mamoru Ishikiriyama , Katsuhito Sasaki
发明人： Mamoru Ishikiriyama , Katsuhito Sasaki
IPC分类号： H01L2358
CPC分类号： H01L29/402
摘要： The present invention provides a semiconductor device capable of improving a withstand voltage for a wire placed in the neighborhood of a contact. When the direction in which a wiring layer extends in the direction of a plane as viewed from the top of a substrate, is defined as a first direction, the direction orthogonal to the first direction on the plane is defined as a second direction, a radius of curvature of a conductive material layer closest to the opening is defined as R, a point where the conductive material layer and an end of the wiring layer intersect, is defined as X, a point where a straight line extending along the second direction from the point X intersects a straight line extending along the first direction through the center of the radius R of curvature of the conductive material layer, is defined as Y, and the distance between the points X and Y as viewed in the second direction is defined as A, the relations in COS−1(A/R)>46 are established.
摘要翻译：本发明提供能够提高放置在接触附近的线的耐受电压的半导体器件。当从衬底的顶部观察布线层沿平面方向延伸的方向被定义为第一方向时，与平面上的第一方向正交的方向被定义为第二方向，半径最靠近开口的导电材料层的曲率被定义为R，其中导电材料层和布线层的一端相交的点被定义为X，其中沿着第二方向延伸的直线点X与沿导体材料层的曲率半径R的中心的沿着第一方向延伸的直线相交，被定义为Y，将从第二方向观察的点X和Y之间的距离定义为A 建立了COS-1（A / R）> 46的关系。

4. 发明申请

US20050035416A1 Semiconductor device with improved protection from electrostatic discharge 有权
标题翻译：具有改进的防静电放电保护的半导体器件
公开(公告)号：US20050035416A1
公开(公告)日：2005-02-17
申请号：US10947329
申请日：2004-09-23
申请人： Toshikazu Kuroda , Katsuhito Sasaki
发明人： Toshikazu Kuroda , Katsuhito Sasaki
IPC分类号： H01L23/528 , H01L23/58 , H01L23/60 , H01L23/62 , H01L29/06 , H01L29/417 , H01L29/78
CPC分类号： H01L23/5286 , H01L23/585 , H01L29/0619 , H01L29/0692 , H01L29/41725 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.
摘要翻译：同心多边形金属氧化物半导体场效应晶体管被设计为避免中心漏极扩散的角和周围环形栅电极的内角之间的重叠。例如，可以通过消除角部来减小栅电极来分离直线段。或者，漏极扩散可以具有十字形状，并且外部环形源极扩散可以被减小到面向十字的端部的直线段，或者源极和漏极扩散和栅电极可以全部被减小以分离直线段。通过避免角区域的电场集中，这些设计提供了增强的防静电放电保护。

5. 发明授权

US07008831B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07008831B2
公开(公告)日：2006-03-07
申请号：US10822752
申请日：2004-04-13
申请人： Katsuhito Sasaki
发明人： Katsuhito Sasaki
IPC分类号： H01L29/41
CPC分类号： H01L29/4983 , H01L21/28105 , H01L29/4238 , H01L29/66492 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a semiconductor device, including forming a gate insulating film on a P type semiconductor layer, forming on the gate insulating film a gate electrode having slits at, at least an end thereof on the drain electrode forming predeterminate side, selectively implanting an N type impurity into the P type semiconductor layer with the gate electrode as a mask, effecting heat treatment to activate the impurity and integrating impurity regions in which the impurity is implanted in the slits and portions outside the gate electrode, by transverse direction thereby to form a pair of N type low-density diffused layers that overlap, at least, on the drain electrode side of the gate electrode, and forming a pair of N type high-density diffused layers spaced away from the gate electrode.
摘要翻译：一种制造半导体器件的方法，包括在P型半导体层上形成栅极绝缘膜，在栅极绝缘膜上形成具有狭缝的栅电极，其至少在端电极形成预定侧，选择性地植入 N型杂质以栅极电极作为掩模进行P型半导体层，进行热处理以使杂质激活，并且通过横向在栅极电极外部的杂质注入杂质区域和积分杂质区域，从而形成至少在栅电极的漏电极侧重叠的一对N型低密度扩散层，形成与栅电极间隔开的一对N型高密度扩散层。

6. 发明授权

US06800528B2 Method of fabricating LDMOS semiconductor devices 失效
标题翻译：制造LDMOS半导体器件的方法
公开(公告)号：US06800528B2
公开(公告)日：2004-10-05
申请号：US10368423
申请日：2003-02-20
申请人： Katsuhito Sasaki
发明人： Katsuhito Sasaki
IPC分类号： H01L21336
CPC分类号： H01L29/7816 , H01L21/28114 , H01L29/42376 , H01L29/66674 , H01L29/7801
摘要： In a method of fabricating an LDMOS semiconductor device, a combined layer including a gate oxide film and a first nitride film is formed on a substrate within a first region. A mask body is formed on the combined layer within a second region that is inside of the first region. Then, first impurities are introduced into the substrate outside of the second region using the mask body as a mask. Next, second impurities are introduced into the substrate outside of the first region using the mask body and the combined layer as a mask. Finally, the introduced first and second impurities are diffused by a heat treatment so as to form a source/drain region and a well region.
摘要翻译：在制造LDMOS半导体器件的方法中，在第一区域内的衬底上形成包括栅极氧化膜和第一氮化物膜的组合层。在第一区域内的第二区域内的组合层上形成掩模体。然后，使用掩模体作为掩模，将第一杂质引入第二区域外的基板。接下来，使用掩模体和组合层作为掩模将第二杂质引入到第一区域外部的基板中。最后，引入的第一和第二杂质通过热处理扩散，以形成源/漏区和阱区。

7. 发明授权

US07521759B2 Semiconductor device, method for manufacturing the same, and gate electrode structure 失效
标题翻译：半导体装置及其制造方法以及栅电极结构
公开(公告)号：US07521759B2
公开(公告)日：2009-04-21
申请号：US11276824
申请日：2006-03-15
申请人： Katsuhito Sasaki
发明人： Katsuhito Sasaki
IPC分类号： H01L29/94
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/402 , H01L29/66659 , H01L29/7833 , H01L29/7835
摘要： A semiconductor structure includes (a) a semiconductor substrate having a channel region and a first integrated impurity diffusion region including a first electric field reduction region that is formed adjacent to the channel region and which includes a plurality of specific regions separated from each other, (b) a first insulating film formed on the semiconductor substrate, and (c) a first electrode structure having a first region formed above the channel region and a second region that is formed adjacent to the first region and above the first electric field reduction region to be self-aligned with the first electric field reduction region, the semiconductor structure including one or more openings formed above the plurality of specific regions and a first opening surrounding portion surrounding the one or more openings.
摘要翻译：半导体结构包括（a）具有沟道区域的半导体衬底和包括与沟道区相邻形成并且包括彼此分离的多个特定区域的第一电场减小区域的第一集成杂质扩散区域（ b）形成在半导体衬底上的第一绝缘膜，和（c）第一电极结构，其具有形成在沟道区上方的第一区域和与第一区域相邻并且形成在第一电场还原区域上方的第二区域，与第一电场还原区域自对准，半导体结构包括形成在多个特定区域上方的一个或多个开口和围绕该一个或多个开口的第一开口围绕部分。

8. 发明授权

US07238991B2 Semiconductor device with improved protection from electrostatic discharge 有权
标题翻译：具有改进的防静电放电保护的半导体器件
公开(公告)号：US07238991B2
公开(公告)日：2007-07-03
申请号：US10947329
申请日：2004-09-23
申请人： Toshikazu Kuroda , Katsuhito Sasaki
发明人： Toshikazu Kuroda , Katsuhito Sasaki
IPC分类号： H01L23/62
CPC分类号： H01L23/5286 , H01L23/585 , H01L29/0619 , H01L29/0692 , H01L29/41725 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.
摘要翻译：同心多边形金属氧化物半导体场效应晶体管被设计为避免中心漏极扩散的角和周围环形栅电极的内角之间的重叠。例如，可以通过消除角部来减小栅电极来分离直线段。或者，漏极扩散可以具有十字形状，并且外部环形源极扩散可以被减小到面向十字的端部的直线段，或者源极和漏极扩散和栅电极可以全部被减小以分离直线段。通过避免角区域的电场集中，这些设计提供了增强的防静电放电保护。

9. 发明授权

US06798022B1 Semiconductor device with improved protection from electrostatic discharge 失效
标题翻译：具有改进的防静电放电保护的半导体器件
公开(公告)号：US06798022B1
公开(公告)日：2004-09-28
申请号：US10384714
申请日：2003-03-11
申请人： Toshikazu Kuroda , Katsuhito Sasaki
发明人： Toshikazu Kuroda , Katsuhito Sasaki
IPC分类号： H01L2362
CPC分类号： H01L23/5286 , H01L23/585 , H01L29/0619 , H01L29/0692 , H01L29/41725 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.
摘要翻译：同心多边形金属氧化物半导体场效应晶体管被设计为避免中心漏极扩散的角和周围环形栅电极的内角之间的重叠。例如，可以通过消除角部来减小栅电极来分离直线段。或者，漏极扩散可以具有十字形状，并且外部环形源极扩散可以被减小到面向十字的端部的直线段，或者源极和漏极扩散和栅电极可以全部被减小以分离直线段。通过避免角区域的电场集中，这些设计提供了增强的防静电放电保护。

10. 发明申请

US20050098838A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050098838A1
公开(公告)日：2005-05-12
申请号：US10822752
申请日：2004-04-13
申请人： Katsuhito Sasaki
发明人： Katsuhito Sasaki
IPC分类号： H01L21/28 , H01L21/336 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/94
CPC分类号： H01L29/4983 , H01L21/28105 , H01L29/4238 , H01L29/66492 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method of manufacturing a semiconductor device, comprising the steps of forming a gate insulating film (102) on a P type semiconductor layer (101), forming on the gate insulating film (102) a gate electrode (103) having slits (104) at, at least one ends thereof on the drain electrode forming predeterminate side, selectively implanting an N type impurity into the P type semiconductor layer (101) with the gate electrode (103) as a mask, effecting heat treatment to activate the impurity and integrating impurity regions in which the impurity is implanted in the slits and portions outside the gate electrode, by transverse direction thereby to form a pair of N type low-density diffused layers (107) that overlap on, at least, on the drain electrode side of the gate electrode, and forming a pair of N type high-density diffused layers (108) with being spaced away from the gate electrode (103).
摘要翻译：本发明提供一种制造半导体器件的方法，包括以下步骤：在P型半导体层（101）上形成栅极绝缘膜（102），在栅绝缘膜（102）上形成栅电极（103）在形成预定侧的漏电极的至少一端处的狭缝（104），以栅电极（103）为掩模，将N型杂质选择性地注入到P型半导体层（101）中，进行热处理以激活通过横向将杂质和杂质注入到狭缝和栅电极外部的杂质和积分杂质区域，从而形成一对N型低密度扩散层（107），其在至少在漏极电极侧，并且与栅电极（103）间隔开形成一对N型高密度扩散层（108）。

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