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1. 发明申请

US20050223241A1 Semiconductor intergrated circuit device, data storage verification device, and data storage verification method 审中-公开
标题翻译：半导体集成电路设备，数据存储验证设备和数据存储验证方法
公开(公告)号：US20050223241A1
公开(公告)日：2005-10-06
申请号：US10517258
申请日：2003-06-13
申请人： Katsuhiro Nakai , Tsuyoshi Nanba , Takehisa Hirano , Tomoaki Tezuka
发明人： Katsuhiro Nakai , Tsuyoshi Nanba , Takehisa Hirano , Tomoaki Tezuka
IPC分类号： G06F21/00 , H04L9/32
CPC分类号： G06F21/572 , G06F21/51
摘要： There is provided a semiconductor integrated circuit device (100) for downloading a program of an arithmetic processing unit, such as a DSP or a CPU, from the outside, wherein a rewrite program as secret information not to be leaked to third parties, which is downloaded in a semiconductor integrated circuit (109), is checked as to whether it is correctly downloaded or not while maintaining the confidentiality of the rewrite program. The semiconductor integrated circuit device is provided with a circuit for verifying the contents of the downloaded rewrite program, and/or a program for verifying the contents of the downloaded rewrite program.
摘要翻译：提供了一种用于从外部下载诸如DSP或CPU的算术处理单元的程序的半导体集成电路装置（100），其中作为不泄漏给第三方的秘密信息的重写程序下载到半导体集成电路（109）中，检查其是否正确下载，同时保持重写程序的机密性。半导体集成电路装置具有用于验证下载的重写程序的内容的电路和/或用于验证下载的重写程序的内容的程序。

2. 发明申请

US20060206689A1 Processor integrated circuit and product development method using the processor integrated circuit 审中-公开
标题翻译：处理器集成电路和产品开发方法采用处理器集成电路
公开(公告)号：US20060206689A1
公开(公告)日：2006-09-14
申请号：US10567373
申请日：2004-08-06
申请人： Takehisa Hirano , Katsuhiro Nakai , Tomoaki Tezuka , Kouji Mukai
发明人： Takehisa Hirano , Katsuhiro Nakai , Tomoaki Tezuka , Kouji Mukai
IPC分类号： G06F9/30
CPC分类号： G06F17/5045 , G06F1/3203 , G06F13/28 , G06F15/7842 , Y02D10/126
摘要： A processor integrated circuit according to the present invention comprises low-speed and high-speed computing units (110), (120) as two or more kinds of computing units, a program memory (131) as a first storage unit in which programs for operation the computing units are stored, a data memory (second storage unit) (132) as a memory area to be used for computation by the computing units, and selectors (141), (142) as first and second connection switching units for connecting a computing unit that performs computation to the first and second storage units, wherein the program memory (131) and the data memory (132) are connected to the low-speed computing unit (110) or the high-speed computing unit (120). In this construction, it is possible to achieve both of securing in program compatibility and speeding-up without increasing the circuit scale and power consumption of the processor integrated circuit.
摘要翻译：根据本发明的处理器集成电路包括作为两种或多种计算单元的低速和高速计算单元（120），（120），作为第一存储单元的程序存储器（131），其中用于存储计算单元的操作，作为要由计算单元计算的存储区域的数据存储器（第二存储单元）（132）和作为用于连接的第一和第二连接切换单元的选择器（141），（142）计算单元，其对所述第一和第二存储单元执行计算，其中所述程序存储器和所述数据存储器连接到所述低速计算单元或所述高速计算单元，。在这种结构中，可以在不增加处理器集成电路的电路规模和功耗的情况下实现程序兼容性和加速的确保。

3. 发明授权

US07780452B2 Individual examination execution device 有权
标题翻译：个人检查执行装置
公开(公告)号：US07780452B2
公开(公告)日：2010-08-24
申请号：US11665658
申请日：2005-10-17
申请人： Kohei Okada , Katsuhiro Nakai , Takehisa Hirano , Kouji Mukai , Tomoaki Tezuka , Daisuke Imoto
发明人： Kohei Okada , Katsuhiro Nakai , Takehisa Hirano , Kouji Mukai , Tomoaki Tezuka , Daisuke Imoto
IPC分类号： G09B11/00
CPC分类号： G09B7/07 , G09B7/077
摘要： In a listening comprehension test using individual examination execution devices, according to the present invention, it is possible to avoid a dishonest act such as peeping at another examinee's answers. An individual examination execution device (101) reads examination question data and individual information from an examination question storage means (102) storing the examination questions and an individual information storage means (103) storing the individual information, respectively. Further, the individual examination device selectively generates actual questions according to the individual information read by an actual question generation means (104), and reproduces the actual questions by a reproduction means (105), thereby preventing dishonest acts of respective examinees.
摘要翻译：在使用个别检查执行装置的听力理解测试中，根据本发明，可以避免不诚实的行为，例如窥视另一个受试者的答案。单独检查执行装置（101）分别从存储检查问题的检查问题存储装置（102）和存储个人信息的个人信息存储装置（103）读取检查问题数据和个人信息。此外，个人检查装置根据由实际问题产生装置（104）读取的个人信息选择性地生成实际问题，并通过再现装置（105）再现实际问题，从而防止各个受试者的不诚实行为。

4. 发明申请

US20100049944A1 Processor integrated circuit and product development method using the processing integrated circuit 审中-公开
标题翻译：处理器集成电路和产品开发方法采用处理集成电路
公开(公告)号：US20100049944A1
公开(公告)日：2010-02-25
申请号：US12588673
申请日：2009-10-23
申请人： Takehisa Hirano , Katsuhiro Nakai , Tomoaki Tezuka , Kouji Mukai
发明人： Takehisa Hirano , Katsuhiro Nakai , Tomoaki Tezuka , Kouji Mukai
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F17/5045 , G06F1/3203 , G06F13/28 , G06F15/7842 , Y02D10/126
摘要： A processor integrated circuit according to the present invention comprises low-speed and high-speed computing units (110), (120) as two or more kinds of computing units, a program memory (131) as a first storage unit in which programs for operation the computing units are stored, a data memory (second storage unit) (132) as a memory area to be used for computation by the computing units, and selectors (141), (142) as first and second connection switching units for connecting a computing unit that performs computation to the first and second storage units, wherein the program memory (131) and the data memory (132) are connected to the low-speed computing unit (110) or the high-speed computing unit (120).In this construction, it is possible to achieve both of securing in program compatibility and speeding-up without increasing the circuit scale and power consumption of the processor integrated circuit.
摘要翻译：根据本发明的处理器集成电路包括作为两种或多种计算单元的低速和高速计算单元（120），（120），作为第一存储单元的程序存储器（131），其中用于存储计算单元的操作，作为要由计算单元计算的存储区域的数据存储器（第二存储单元）（132）和作为用于连接的第一和第二连接切换单元的选择器（141），（142）计算单元，其对所述第一和第二存储单元执行计算，其中所述程序存储器和所述数据存储器连接到所述低速计算单元或所述高速计算单元，。在这种结构中，可以在不增加处理器集成电路的电路规模和功耗的情况下实现程序兼容性和加速的确保。

5. 发明申请

US20080020366A1 Individual Examination Execution Device 有权
标题翻译：个人考试执行机构
公开(公告)号：US20080020366A1
公开(公告)日：2008-01-24
申请号：US11665658
申请日：2005-10-17
申请人： Kohei Okada , Katsuhiro Nakai , Takehisa Hirano , Kouji Mukai , Tomoaki Tezuka , Daisuke Imoto
发明人： Kohei Okada , Katsuhiro Nakai , Takehisa Hirano , Kouji Mukai , Tomoaki Tezuka , Daisuke Imoto
IPC分类号： G09B7/00
CPC分类号： G09B7/07 , G09B7/077
摘要： In a listening comprehension test using individual examination execution devices, it is possible to avoid a dishonest act such as peeping at another examinee's answers. In an individual examination execution device (101), examination question data and individual information are read from an examination question storage means (102) that stores the examination questions and an individual information storage means (103) that stores the individual information, respectively, and actual questions that are selectively generated according to the individual information read by an actual question generation means (104) are reproduced by a reproduction means (105), thereby preventing dishonest acts of the respective examinees.
摘要翻译：在使用个人检查执行装置的听力理解测试中，可以避免不诚实的行为，例如窥视另一个受试者的答案。在单独检查执行装置（101）中，分别从存储检查问题的检查问题存储装置（102）和存储个人信息的个人信息存储装置（103）读取检查问题数据和个人信息，以及根据由实际问题产生装置（104）读取的个人信息选择性地生成的实际问题由再现装置（105）再现，从而防止各个受试者的不诚实行为。

6. 发明申请

US20070275361A1 Individual Examination Execution Device 审中-公开
标题翻译：个人考试执行机构
公开(公告)号：US20070275361A1
公开(公告)日：2007-11-29
申请号：US10593873
申请日：2005-03-11
申请人： Tomoaki Tezuka , Katsuhiro Nakai , Takehisa Hirano , Kouji Mukai
发明人： Tomoaki Tezuka , Katsuhiro Nakai , Takehisa Hirano , Kouji Mukai
IPC分类号： G09B3/00
CPC分类号： G09B5/04 , G09B7/02
摘要： An individual examination execution device is provided with a question storage means (14) in which exam questions are stored, a sequence data holding means (12) that holds sequence data as a basis of exam question reproduction sequence, at sequence instruction means (13) for reading the exam questions stored in the question storage means (14), and a reproduction means (15) for reproducing the exam questions stored in the question storage means (14) into audio. The sequence instruction means (13) reads the exam questions stored in the question storage means (14) with reference to the sequence data stored in the sequence data holding means (12), and the exam question reproduction sequence is changed according to the seat position.
摘要翻译：个体检查执行装置具有存储检查问题的问题存储装置（14），在序列指令装置（13）处存储作为检查问题再现序列的基础的序列数据的序列数据保持装置（12）用于阅读存储在问题存储装置（14）中的考试问题，以及用于将存储在问题存储装置（14）中的考试题目再现成音频的再现装置（15）。序列指示装置（13）参照存储在序列数据保持装置（12）中的序列数据，读出存储在问题存储装置（14）中的检查问题，并且根据座位位置改变检查问题再现顺序。

7. 发明授权

US06243073B1 Video display monitor 失效
标题翻译：视频显示器
公开(公告)号：US06243073B1
公开(公告)日：2001-06-05
申请号：US08986504
申请日：1997-12-08
申请人： Hideaki Kawamura , Mitsuhiro Kasahara , Kazuo Ohira , Takehisa Hirano , Katsuhiro Nakai
发明人： Hideaki Kawamura , Mitsuhiro Kasahara , Kazuo Ohira , Takehisa Hirano , Katsuhiro Nakai
IPC分类号： G09G510
CPC分类号： G09G3/2022 , G09G3/282 , G09G2310/0205 , G09G2310/0216 , G09G2320/0247
摘要： A video display monitor, such as a plasma monitor, which uses a subfield method which overlaps weighted multiple binary video images in a time base for display. The stable driving of a plasma display panel may be assured and display in the 256 grey-level may be maintained although vertical synchronizing frequency of the input video signal changes. A vertical synchronizing measurement unit measures the vertical synchronizing frequency of the video signal, and a subfield number adjustment unit adjusts the number of subfields in accordance with a measured vertical synchronizing frequency. The stable driving of the plasma display panel and display in grey levels may be assured by selecting a ROM table with an output bit width equivalent to the number of subfields to be output from multiple ROM tables used for converting the number of bits in the input signal.
摘要翻译：诸如等离子体监视器的视频显示监视器，其使用在时基中重叠加权的多个二进制视频图像以进行显示的子场方法。可以确保等离子体显示面板的稳定驱动，并且即使输入视频信号的垂直同步频率发生变化，也可以维持256灰度级的显示。垂直同步测量单元测量视频信号的垂直同步频率，子场数调整单元根据所测量的垂直同步频率来调整子场数。等离子体显示面板的稳定驱动和灰度级显示可以通过选择具有等于从用于转换输入信号中的位数的多个ROM表中输出的子场数量的ROM表来确保。

8. 发明授权

US08495268B2 Card host LSI and set device including the same 有权
标题翻译：卡主机LSI和集成设备包括相同
公开(公告)号：US08495268B2
公开(公告)日：2013-07-23
申请号：US12861569
申请日：2010-08-23
申请人： Takehisa Hirano , Makoto Fujiwara , Koichiro Fue , Rie Itou , Kentaro Shiomi
发明人： Takehisa Hirano , Makoto Fujiwara , Koichiro Fue , Rie Itou , Kentaro Shiomi
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/385
摘要： In a set device having a card host LSI, high-speed data transmission to a removable card or the like is realized without hindering a reduction in size and weight. The card host LSI and the removable card are connected to a card bus complying with predetermined card bus specifications. A microcomputer module and the card host LSI are connected also by a card bus complying with the predetermined card bus specifications.
摘要翻译：在具有卡主机LSI的集合装置中，实现了到可移除卡等的高速数据传输，而不会妨碍尺寸和重量的减小。卡主机LSI和可拆卸卡连接到符合预定卡总线规格的卡总线。微型计算机模块和卡主机LSI也通过符合预定卡总线规格的卡总线连接。

9. 发明申请

US20100318690A1 CARD HOST LSI AND SET DEVICE INCLUDING THE SAME 有权
标题翻译：卡主机LSI和集成设备，包括它们
公开(公告)号：US20100318690A1
公开(公告)日：2010-12-16
申请号：US12861569
申请日：2010-08-23
申请人： Takehisa Hirano , Makoto Fujiwara , Koichiro Fue , Rie Itou , Kentaro Shiomi
发明人： Takehisa Hirano , Makoto Fujiwara , Koichiro Fue , Rie Itou , Kentaro Shiomi
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/385
摘要： In a set device having a card host LSI, high-speed data transmission to a removable card or the like is realized without hindering a reduction in size and weight. The card host LSI and the removable card are connected to a card bus complying with predetermined card bus specifications. A microcomputer module and the card host LSI are connected also by a card bus complying with the predetermined card bus specifications.
摘要翻译：在具有卡主机LSI的集合装置中，实现了到可移除卡等的高速数据传输，而不会妨碍尺寸和重量的减小。卡主机LSI和可拆卸卡连接到符合预定卡总线规格的卡总线。微型计算机模块和卡主机LSI也通过符合预定卡总线规格的卡总线连接。

10. 发明申请

US20110197008A1 CARD HOST LSI AND SET DEVICE INCLUDING THE LSI 审中-公开
标题翻译：卡主机LSI和设置包括LSI的设备
公开(公告)号：US20110197008A1
公开(公告)日：2011-08-11
申请号：US13089985
申请日：2011-04-19
申请人： Rie ITOU , Makoto Fujiwara , Takehisa Hirano , Koichiro Fue
发明人： Rie ITOU , Makoto Fujiwara , Takehisa Hirano , Koichiro Fue
IPC分类号： G06F13/14
CPC分类号： G06F13/4081
摘要： A card host LSI includes M card host I/Fs for N-bit card modules, and M card bus terminals. A bridge circuit sets coupling relationship of signal lines so that a card host I/F corresponding to a card bus coupled to an (M×N)-bit card module and the other card host I/F(s) operate in conjunction with each other to control the card module, when an enable signal indicates the (M×N)-bit mode.
摘要翻译：卡主机LSI包括用于N位卡模块的M卡主机I / F和M卡总线端子。桥接电路设置信号线的耦合关系，使得对应于耦合到（M×N）位卡模块和另一个卡主机I / F的卡总线的卡主机I / F与每个其他控制卡模块，当使能信号指示（M×N）位模式时。

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