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1. 发明授权

US06865508B2 Log analysis method and recording medium storing log analysis program 失效
标题翻译：日志分析方法和记录介质存储日志分析程序
公开(公告)号：US06865508B2
公开(公告)日：2005-03-08
申请号：US10329397
申请日：2002-12-27
申请人： Katsuhiko Ueki , Humitaka Tamura , Wataru Okamoto , Masayuki Hirayama
发明人： Katsuhiko Ueki , Humitaka Tamura , Wataru Okamoto , Masayuki Hirayama
IPC分类号： G06F11/34 , G06F11/36 , G06F17/18 , G06F19/00
CPC分类号： G06F11/3616
摘要： One of log analysis methods of the present invention includes the step of executing a program a plurality of times; executing a program a plurality of times; the step of generating a plurality of logs, each log being recorded a plurality of events occurring upon the execution of the program according to an occurrence order of each of the events in each of the logs; the step of performing a first calculation to calculate an event occurrence probability, for the occurrence order of each event, based on at least one from the program description concerning each event recorded in the logs and the data to be used upon the execution of the program description; and the step of outputting information concerning an event which corresponds to a characteristic included in the logs, based on the event occurrence probability.
摘要翻译：本发明的对数分析方法之一包括执行程序多次的步骤; 执行程序多次; 生成多个日志的步骤，每个日志根据每个日志中的每个事件的发生顺序记录在执行程序时发生的多个事件; 基于关于记录在日志中的每个事件的程序描述和在程序执行中使用的数据中的至少一个，执行每个事件的发生顺序的事件发生概率的计算事件发生概率的步骤描述; 以及基于事件发生概率输出关于与包括在日志中的特征相对应的事件的信息的步骤。

2. 发明授权

US07050942B2 Object state classification method and system, and program therefor 失效
标题翻译：对象状态分类方法和系统及其程序
公开(公告)号：US07050942B2
公开(公告)日：2006-05-23
申请号：US10736705
申请日：2003-12-17
申请人： Masayuki Hirayama , Katsuhiko Ueki , Wataru Okamoto
发明人： Masayuki Hirayama , Katsuhiko Ueki , Wataru Okamoto
IPC分类号： G06F19/00
CPC分类号： G06F11/3676
摘要： An object state classification method includes a step of designating a to-be-determined object that is to be determined, and a state of the to-be-determined object, a step of creating a method set including, as elements, methods called from the designated state of the to-be-determined object, a step of using, as a to-be-determined state, the designated state of the to-be-determined object or another state obtained by calling methods from the designated state, and executing a program for calling methods included in the method set from the to-be-determined state, a step of recording an execution result in a case of calling the methods, and a step of creating a pseudo-state by merging a method group that is the elements of the method set, and the execution result in the case of calling each method of the method group, in association with the to-be-determined state of the to-be-determined object.
摘要翻译：目标状态分类方法包括指定要确定的待定对象的步骤和待确定对象的状态，创建方法集合的步骤，该方法集合包括作为从要确定的对象的指定状态，将待确定对象的指定状态或通过从指定状态调用方法获得的另一状态用作待定状态的步骤，以及执行用于调用从待确定状态设置的方法中包括的方法的程序，在调用方法的情况下记录执行结果的步骤，以及通过合并方法组来创建伪状态的步骤，是方法集的元素，以及在要被确定的对象的待定状态的情况下调用方法组的每个方法的情况下的执行结果。

3. 发明授权

US07616516B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07616516B2
公开(公告)日：2009-11-10
申请号：US12109339
申请日：2008-04-24
申请人： Masayuki Hirayama , Masami Hasegawa , Michitaro Kanamitsu , Yayoi Hayashi , Naoyuki Anan
发明人： Masayuki Hirayama , Masami Hasegawa , Michitaro Kanamitsu , Yayoi Hayashi , Naoyuki Anan
IPC分类号： G11C5/14
CPC分类号： G11C11/412
摘要： A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.
摘要翻译：本发明的半导体器件具有在多个字线和多个互补位线的交叉部分设置有多个CMOS静态存储单元的存储单元阵列。在存储单元阵列中，开关MOSFET在与第一操作模式不同的第一操作模式和第二操作模式中处于断开状态，并且具有第一导电类型和第二导电类型的MOSFET，其具有在构成构成多个静态存储单元的第一和第二CMOS反相器电路的第一导电型MOSFET的源极连接到的第一源极线和与第一源极线对应的第一电源线之间并联设置二极管配置。构成第一和第二CMOS反相器电路的第二导电型MOSFET的源极连接的第二源极线连接到与其对应的第二电源线。

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