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1. 发明授权

US09658829B2 Near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine 有权
公开(公告)号：US09658829B2
公开(公告)日：2017-05-23
申请号：US12581482
申请日：2009-10-19
申请人： Karthikeyan Vaithianathan , Arvind Sudarsanam
发明人： Karthikeyan Vaithianathan , Arvind Sudarsanam
IPC分类号： G06F7/50 , G06F7/544 , G06F17/10 , G06F7/508 , G06F7/505
CPC分类号： G06F7/544 , G06F7/505 , G06F7/508 , G06F17/10 , G06F2207/5442
摘要： Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network.

2. 发明申请

US20110093518A1 NEAR OPTIMAL CONFIGURABLE ADDER TREE FOR ARBITRARY SHAPED 2D BLOCK SUM OF ABSOLUTE DIFFERENCES (SAD) CALCULATION ENGINE 有权
标题翻译：邻近的最佳配置ADDER TREE用于绝对形状二维块的绝对差异（SAD）计算引擎
公开(公告)号：US20110093518A1
公开(公告)日：2011-04-21
申请号：US12581482
申请日：2009-10-19
申请人： Karthikeyan Vaithianathan , Arvind Sudarsanam
发明人： Karthikeyan Vaithianathan , Arvind Sudarsanam
IPC分类号： G06F7/50
CPC分类号： G06F7/544 , G06F7/505 , G06F7/508 , G06F17/10 , G06F2207/5442
摘要： Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network.
摘要翻译：这里通常描述用于任意形状的2D块绝对差（SAD）计算引擎的近似最佳可配置加法器树的实施例。可以描述和要求保护其他实施例。在一些实施例中，用于计算高达16×16的各种块大小的绝对差（SAD）之和的可配置二维加法器树结构包括一维加法器树的第一级和一维加法器的第二级树，其中每个一维加法器树包括输入路由网络，多个加法器单元和输出路由网络。

3. 发明申请

US20070198971A1 Reconfigurable processing 有权
标题翻译：可重构处理
公开(公告)号：US20070198971A1
公开(公告)日：2007-08-23
申请号：US10544894
申请日：2004-02-05
申请人： Aravind Dasu , Ali Akoglu , Arvind Sudarsanam , Sethuraman Panchanathan
发明人： Aravind Dasu , Ali Akoglu , Arvind Sudarsanam , Sethuraman Panchanathan
IPC分类号： G06F9/45
CPC分类号： G06F8/433 , G06F8/4432 , G06F17/5045 , Y02D10/41
摘要： A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed. Scheduling of the overall code is effected for sequencing, providing fastest run times and the code is implemented in hardware by partitioning and placement of processing elements on a chip and design of the connective fabric for the design elements.
摘要翻译：一种用于运行诸如多媒体处理等中等复杂度的计算机程序的可重构电路装置的方法。应用程序的代码被编译成表示要运行的应用程序的不同部分的控制流图。从这些控制流图中提取基本块。基本块由编译器实用程序转换为数据流图。从两个或更多数据流图，确定最大的公共子图。最大的公共子图是ASAP预定的，并被替换为也被安排的数据流图。包含预定最大公共子图的单独数据流图被转换为数据路径，然后将其组合以形成用于操作应用程序的代码。最大的共同子图是在开发数据流图的应用程序部分之间共享的硬件实现的。总体代码的调度受到排序的影响，提供最快的运行时间，并且代码通过在处理元件上分配和放置芯片以及为设计元素设计的连接结构来实现。

4. 发明授权

US08281297B2 Reconfigurable processing 有权
标题翻译：可重构处理
公开(公告)号：US08281297B2
公开(公告)日：2012-10-02
申请号：US10544894
申请日：2004-02-05
申请人： Aravind R. Dasu , Ali Akoglu , Arvind Sudarsanam , Sethuraman Panchanathan
发明人： Aravind R. Dasu , Ali Akoglu , Arvind Sudarsanam , Sethuraman Panchanathan
IPC分类号： G06F9/45
CPC分类号： G06F8/433 , G06F8/4432 , G06F17/5045 , Y02D10/41
摘要： A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed. Scheduling of the overall code is effected for sequencing, providing fastest run times and the code is implemented in hardware by partitioning and placement of processing elements on a chip and design of the connective fabric for the design elements.
摘要翻译：一种用于运行诸如多媒体处理等中等复杂度的计算机程序的可重构电路装置的方法。应用程序的代码被编译成表示要运行的应用程序的不同部分的控制流图。从这些控制流图中提取基本块。基本块由编译器实用程序转换为数据流图。从两个或更多数据流图，确定最大的公共子图。最大的公共子图是ASAP预定的，并被替换为也被安排的数据流图。包含预定最大公共子图的单独数据流图被转换为数据路径，然后将其组合以形成用于操作应用程序的代码。最大的共同子图是在开发数据流图的应用程序部分之间共享的硬件实现的。总体代码的调度受到排序的影响，提供最快的运行时间，并且代码通过在处理元件上分配和放置芯片以及为设计元素设计的连接结构来实现。

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