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1. 发明申请

US20120132981A1 SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储器件的半导体存储器件和制造方法
公开(公告)号：US20120132981A1
公开(公告)日：2012-05-31
申请号：US13112345
申请日：2011-05-20
申请人： Takeshi Imamura , Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Ryouhei Kirisawa
发明人： Takeshi Imamura , Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Ryouhei Kirisawa
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L27/11556 , H01L29/42324 , H01L29/7889
摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.
摘要翻译：根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

2. 发明授权

US08598643B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08598643B2
公开(公告)日：2013-12-03
申请号：US13235425
申请日：2011-09-18
申请人： Kaori Kawasaki , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
发明人： Kaori Kawasaki , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层，绝缘构件和硅化物层。存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

3. 发明授权

US08766351B2 Semiconductor storage device and manufacturing method of semiconductor storage device 有权
标题翻译：半导体存储装置及半导体存储装置的制造方法
公开(公告)号：US08766351B2
公开(公告)日：2014-07-01
申请号：US13112345
申请日：2011-05-20
申请人： Takeshi Imamura , Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Ryouhei Kirisawa
发明人： Takeshi Imamura , Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Ryouhei Kirisawa
IPC分类号： H01L29/788
CPC分类号： H01L27/11556 , H01L29/42324 , H01L29/7889
摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.
摘要翻译：根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

4. 发明申请

US20120241846A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120241846A1
公开(公告)日：2012-09-27
申请号：US13235425
申请日：2011-09-18
申请人： Kaori KAWASAKI , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
发明人： Kaori KAWASAKI , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层，绝缘构件和硅化物层。存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

5. 发明授权

US08582341B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08582341B2
公开(公告)日：2013-11-12
申请号：US13424552
申请日：2012-03-20
申请人： Yoshiaki Fukuzumi , Takeshi Imamura , Hideaki Aochi
发明人： Yoshiaki Fukuzumi , Takeshi Imamura , Hideaki Aochi
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C5/02 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole.
摘要翻译：根据实施例，制造包括设置在基板上的存储器阵列的半导体器件的方法以及设置在衬底和存储器阵列之间的衬底的表面上的控制电路包括以下步骤：在绝缘层覆盖控制电路的p型半导体区域和n型半导体区域，与p型半导体区域连通的第一接触孔; 在所述第一接触孔内形成与所述p型半导体区域接触的接触插塞; 在所述绝缘层中形成与所述n型半导体区域连通的第二接触孔; 以及形成接触所述接触插塞和暴露在所述第二接触孔内的所述n型半导体区域的互连。

6. 发明申请

US20130070508A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130070508A1
公开(公告)日：2013-03-21
申请号：US13424552
申请日：2012-03-20
申请人： Yoshiaki Fukuzumi , Takeshi Imamura , Hideaki Aochi
发明人： Yoshiaki Fukuzumi , Takeshi Imamura , Hideaki Aochi
IPC分类号： G11C5/06 , H01L21/822
CPC分类号： G11C5/06 , G11C5/02 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole.
摘要翻译：根据实施例，制造包括设置在基板上的存储器阵列的半导体器件的方法以及设置在衬底和存储器阵列之间的衬底的表面上的控制电路包括以下步骤：在绝缘层覆盖控制电路的p型半导体区域和n型半导体区域，与p型半导体区域连通的第一接触孔; 在所述第一接触孔内形成与所述p型半导体区域接触的接触插塞; 在所述绝缘层中形成与所述n型半导体区域连通的第二接触孔; 以及形成接触所述接触插塞和暴露在所述第二接触孔内的所述n型半导体区域的互连。

7. 发明授权

US08692312B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08692312B2
公开(公告)日：2014-04-08
申请号：US13428506
申请日：2012-03-23
申请人： Yoshiaki Fukuzumi , Masaru Kito , Takeshi Imamura
发明人： Yoshiaki Fukuzumi , Masaru Kito , Takeshi Imamura
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11582 , H01L29/66833
摘要： According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer.
摘要翻译：根据一个实施例，提供一种制造半导体存储器件的方法。在该方法中，形成依次层叠有第一硅层，第一牺牲层，第二硅层和第二牺牲层的层叠体。第一绝缘膜形成在层叠体上。在层叠体和第一绝缘膜中形成沟槽。第三牺牲层形成在沟槽中。通过湿蚀刻蚀刻第三牺牲层以从第三牺牲层的顶表面撤回，从而蚀刻第一牺牲层和第二牺牲层的端面。

8. 发明申请

US20130062683A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20130062683A1
公开(公告)日：2013-03-14
申请号：US13428506
申请日：2012-03-23
申请人： Yoshiaki FUKUZUMI , Masaru Kito , Takeshi Imamura
发明人： Yoshiaki FUKUZUMI , Masaru Kito , Takeshi Imamura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11582 , H01L29/66833
摘要： According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer.
摘要翻译：根据一个实施例，提供一种制造半导体存储器件的方法。在该方法中，形成依次层叠有第一硅层，第一牺牲层，第二硅层和第二牺牲层的层叠体。第一绝缘膜形成在层叠体上。在层叠体和第一绝缘膜中形成沟槽。第三牺牲层形成在沟槽中。通过湿蚀刻蚀刻第三牺牲层以从第三牺牲层的顶表面撤回，从而蚀刻第一牺牲层和第二牺牲层的端面。

9. 发明授权

US08131787B2 Information, transformation and reverse transformation processing 失效
标题翻译：信息，转型和逆向转换处理
公开(公告)号：US08131787B2
公开(公告)日：2012-03-06
申请号：US12123991
申请日：2008-05-20
申请人： Takeshi Imamura , Kent Tamura , Satoshi Makino , Toshiro Takase
发明人： Takeshi Imamura , Kent Tamura , Satoshi Makino , Toshiro Takase
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/227 , Y10S707/99942
摘要： A transformation processing system input data including a data record area for storing target date and a transformation processing identification information record area for storing transformation processing identification information about transformation processing executed upon the target data. The transformation processing system includes: a reverse transformation information recording unit which records a target data pointer indicating the data record area in transformed data, a transformation processing identification information pointer indicating the transformation processing identification information record area, and reverse transformation processing identification information about reverse transformation processing; a target data transformation unit which transforms the target data and records it in the data record area; and a transformation processing identification information recording unit which adds the transformation processing identification information about the transformation processing executed by the target data transformation unit to the transformation processing identification information record area in the input data.
摘要翻译：变换处理系统输入数据，包括用于存储目标日期的数据记录区域和用于存储关于在目标数据上执行的变换处理的变换处理识别信息的变换处理识别信息记录区域。变换处理系统包括：逆变换信息记录单元，其在变换数据中记录指示数据记录区的目标数据指针，指示变换处理识别信息记录区的变换处理识别信息指针，以及反转变换处理识别信息转换处理; 目标数据变换单元，其转换目标数据并将其记录在数据记录区域中; 以及变换处理识别信息记录单元，其将关于由目标数据变换单元执行的变换处理的变换处理识别信息添加到输入数据中的变换处理识别信息记录区域。

10. 发明授权

US07919263B2 Organic material-immobiling structure and method for production of the same, and peptide and DNA therefor 失效
标题翻译：有机材料固定结构及其生产方法，以及肽和DNA
公开(公告)号：US07919263B2
公开(公告)日：2011-04-05
申请号：US10548442
申请日：2004-08-18
申请人： Hidenori Shiotsuka , Takeshi Imamura , Tsuyoshi Nomoto , Miki Ogawa
发明人： Hidenori Shiotsuka , Takeshi Imamura , Tsuyoshi Nomoto , Miki Ogawa
IPC分类号： G01N31/00 , G01N33/53
CPC分类号： C07K17/14 , C07K7/08 , C07K17/08 , C12N11/14 , G01N33/54353 , G01N33/552
摘要： The invention provides an organic material-immobilizing structure employing new immobilization means, characterized in that at least a part of the surface of the substrate is comprised of one or more members containing silicon oxide, the organic material is bound to the surface of the substrate through a binding domain bound to the organic material and containing an amino acid sequence capable of binding to silicon oxide, selected from the group consisting of amino acid sequences of SEQ ID NOS: 1 and 2: Val-Ser-Pro-Met-Arg-Ser-Ala-Thr-Thr-His-Thr-Val; and Ile-Pro-Met-His-Val-His-His-Lys-His-Pro-His-Val, and derivatives thereof.
摘要翻译：本发明提供一种使用新的固定装置的有机材料固定结构，其特征在于，基底表面的至少一部分由含有氧化硅的一种或多种构件组成，有机材料通过与有机材料结合并含有能够结合氧化硅的氨基酸序列的结合结构域，其选自SEQ ID NO：1和2的氨基酸序列：Val-Ser-Pro-Met-Arg-Ser -Ala-Thr-Thr-His-Thr-Val; 和Ile-Pro-Met-His-Val-His-His-Lys-His-Pro-His-Val及其衍生物。

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