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1. 发明申请

US20120327728A1 METHOD AND APPARATUS FOR MEMORY COMMAND INPUT AND CONTROL 有权
标题翻译：用于存储器命令输入和控制的方法和装置
公开(公告)号：US20120327728A1
公开(公告)日：2012-12-27
申请号：US13168723
申请日：2011-06-24
申请人： Jacob Robert Anderson , Kang-Yong Kim , Tadashi Yamamoto , Zer Liang , Huy Vo
发明人： Jacob Robert Anderson , Kang-Yong Kim , Tadashi Yamamoto , Zer Liang , Huy Vo
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G06F13/4234 , G11C7/00 , G11C7/10 , Y02D10/14 , Y02D10/151
摘要： Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.
摘要翻译：公开了包含命令解码器，芯片使能和信号截断电路的存储器。一个这样的命令解码器电路可以包括命令解码器逻辑，其被配置为接收命令信号，并且响应于具有活动状态的片选信号而将解码的命令输出到互连总线。解码器电路还可以基于接收到具有无效状态的片选信号来防止到互连总线的耦合命令。存储器还可以包括具有控制逻辑的芯片使能电路，其配置成接收芯片选择信号并且响应于接收到有效命令而将芯片选择信号提供给互连总线。芯片使能电路还可以基于无效命令信号的接收，防止从芯片使能信号将互连芯片选择信号耦合到互连总线。信号截断电路可用于缩短和/或移位芯片选择信号以增加定时裕度并提高存储器执行命令的可靠性。

2. 发明授权

US08913447B2 Method and apparatus for memory command input and control 有权
标题翻译：用于存储器命令输入和控制的方法和装置
公开(公告)号：US08913447B2
公开(公告)日：2014-12-16
申请号：US13168723
申请日：2011-06-24
申请人： Jacob Robert Anderson , Kang-Yong Kim , Tadashi Yamamoto , Zer Liang , Huy Vo
发明人： Jacob Robert Anderson , Kang-Yong Kim , Tadashi Yamamoto , Zer Liang , Huy Vo
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G06F13/4234 , G11C7/00 , G11C7/10 , Y02D10/14 , Y02D10/151
摘要： Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.
摘要翻译：公开了包含命令解码器，芯片使能和信号截断电路的存储器。一个这样的命令解码器电路可以包括命令解码器逻辑，其被配置为接收命令信号，并且响应于具有活动状态的片选信号而将解码的命令输出到互连总线。解码器电路还可以基于接收到具有无效状态的片选信号来防止到互连总线的耦合命令。存储器还可以包括具有控制逻辑的芯片使能电路，其配置成接收芯片选择信号并且响应于接收到有效命令而将芯片选择信号提供给互连总线。芯片使能电路还可以基于无效命令信号的接收，防止从芯片使能信号将互连芯片选择信号耦合到互连总线。信号截断电路可用于缩短和/或移位芯片选择信号以增加定时裕度并提高存储器执行命令的可靠性。

3. 发明授权

US08499187B2 Methods and apparatuses for master-slave detection 有权
标题翻译：主从检测方法和装置
公开(公告)号：US08499187B2
公开(公告)日：2013-07-30
申请号：US13209234
申请日：2011-08-12
申请人： Kang-Yong Kim , Jacob Robert Anderson , Huy Vo
发明人： Kang-Yong Kim , Jacob Robert Anderson , Huy Vo
IPC分类号： G06F1/14
CPC分类号： G11C7/20 , G11C29/003 , G11C29/32 , G11C29/50012 , G11C2029/0407 , H01L25/0657
摘要： Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.
摘要翻译：公开了设备，主 - 从检测电路，存储器和方法。一种这样的方法包括执行主检测阶段，在此期间，将存储器组中的存储器单元确定为主存储器单元，在每个存储器单元处确定其相对于其他存储器单元的位置，以及在每个存储器单元处确定其位于存储器组基于从属存储器单元的总数及其相对于其他存储器单元的位置。

4. 发明申请

US20130042138A1 METHODS AND APPARATUSES FOR MASTER-SLAVE DETECTION 有权
公开(公告)号：US20130042138A1
公开(公告)日：2013-02-14
申请号：US13209234
申请日：2011-08-12
申请人： Kang-Yong Kim , Jacob Robert Anderson , Huy Vo
发明人： Kang-Yong Kim , Jacob Robert Anderson , Huy Vo
IPC分类号： G06F1/14
CPC分类号： G11C7/20 , G11C29/003 , G11C29/32 , G11C29/50012 , G11C2029/0407 , H01L25/0657
摘要： Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

5. 发明授权

US06434079B1 Semiconductor memory device for distributing load of input and output lines 有权
公开(公告)号：US06434079B1
公开(公告)日：2002-08-13
申请号：US09746142
申请日：2000-12-21
申请人： Kang-Yong Kim
发明人： Kang-Yong Kim
IPC分类号： G11C800
摘要： A semiconductor memory device for distributing load of input and output lines includes: a line pre-charger for pre-charging a global read line composed of a pair of lines to a high level in an initial or steady state, a plurality of memory banks connected to a global write line for storing data provided thereto, each of which includes a memory cell array composed of a number of memory cells coupled to a multiplicity of sense amplifiers and the multiplicity of write drivers, a number of multiplexers for selecting the data from the read line; and a data input multiplexer for providing externally inputted data to the global write line on the write operation.

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