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1. 发明申请

US20060102197A1 Post-etch treatment to remove residues 审中-公开
标题翻译：蚀刻后处理以除去残留物
公开(公告)号：US20060102197A1
公开(公告)日：2006-05-18
申请号：US10989678
申请日：2004-11-16
申请人： Kang-Lie Chiang , Man-Ping Cai , Shawming Ma , Yan Ye , Peter Hsieh
发明人： Kang-Lie Chiang , Man-Ping Cai , Shawming Ma , Yan Ye , Peter Hsieh
IPC分类号： B08B6/00 , B08B5/04
CPC分类号： C23F4/00 , B08B7/00 , H01L21/02063 , H01L21/31116 , H01L21/76808 , H01L21/76814
摘要： A method for removing residue from a layer of conductive material on a substrate is provided herein. In one embodiment, the method includes introducing a process gas into a vacuum chamber having a substrate surface with residue from exposure to a fluorine-containing environment. The process gas includes a hydrogen-containing gas. Optionally, the process gas may further include an oxygen-containing or a nitrogen containing gas. A plasma of the process gas is thereafter maintained in the vacuum chamber for a predetermined period of time to remove the residue from the surface. The temperature of the substrate is maintained at a temperature between about 10 degrees Celsius and about 90 degrees Celsius during the plasma step.
摘要翻译：本文提供了用于从基底上的导电材料层除去残余物的方法。在一个实施方案中，该方法包括将工艺气体引入真空室，该真空室具有残留物暴露于含氟环境的基底表面。工艺气体包括含氢气体。任选地，工艺气体还可以包括含氧气体或含氮气体。然后将该工艺气体的等离子体在真空室中保持预定的时间以从表面除去残余物。在等离子体步骤期间，基板的温度保持在约10摄氏度和约90摄氏度之间的温度。

2. 发明申请

US20090023294A1 METHOD FOR ETCHING USING ADVANCED PATTERNING FILM IN CAPACITIVE COUPLING HIGH FREQUENCY PLASMA DIELECTRIC ETCH CHAMBER 审中-公开
标题翻译：电容耦合高频等离子体电介质隔室中使用高级图案薄膜的蚀刻方法
公开(公告)号：US20090023294A1
公开(公告)日：2009-01-22
申请号：US11778239
申请日：2007-07-16
申请人： JUDY WANG , Shing-Li Sung , Shawming Ma
发明人： JUDY WANG , Shing-Li Sung , Shawming Ma
IPC分类号： H01L21/461
CPC分类号： H01L21/31122 , H01L21/31116 , H01L21/31144
摘要： A method for etching wafers using advanced patterning film (APF) to reduce bowing and improve bottom-to-top ratios includes providing a wafer having an APF layer into a processing chamber, wherein the processing chamber is configured with a power source operating at about 162 MHz, supplying a process gas into the chamber, applying a source power using the 162 MHz power source, and applying a bias power to the wafer. The process gas comprises hydrogen gas (H2), nitrogen gas (N2), and carbon monoxide gas (CO). The ratio of H2:N2 is about 1:1. Additionally, the wafer temperature is adjusted to improve the etching characteristics.
摘要翻译：使用先进的图案形成薄膜（APF）来蚀刻晶片以减少弯曲并改善底部对顶部比率的方法包括将具有APF层的晶片提供到处理室中，其中处理室配置有操作大约162的电源将工艺气体供应到腔室中，使用162MHz的电源施加源电力，并向晶片施加偏置功率。工艺气体包括氢气（H 2），氮气（N 2）和一氧化碳气体（CO）。 H2：N2的比例约为1:1。此外，调整晶片温度以改善蚀刻特性。

3. 发明申请

US20070077780A1 Process to open carbon based hardmask 失效
标题翻译：开放碳基硬掩模的工艺
公开(公告)号：US20070077780A1
公开(公告)日：2007-04-05
申请号：US11244422
申请日：2005-10-05
申请人： Judy Wang , Shing-Li Sung , Shawming Ma , Bryan Pu
发明人： Judy Wang , Shing-Li Sung , Shawming Ma , Bryan Pu
IPC分类号： H01L21/31 , H01L21/469 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01J37/32082 , H01J37/32165 , H01J37/3266 , H01L21/31122
摘要： A method of opening a carbon-based hardmask layer composed of amorphous carbon containing preferably at least 60% carbon and between 10 and 40% hydrogen. The hardmask is opened by plasma etching using an etching gas composed of H2, N2, and CO. The etching is preferably performed in a plasma etch reactor having an HF biased pedestal electrode and a capacitively VHF biased showerhead.
摘要翻译：一种由优选含有至少60％的碳和10至40％氢气的无定形碳组成的碳基硬掩模层的方法。使用由H 2 N 2 N 2 N 2和CO组成的蚀刻气体通过等离子体蚀刻来打开硬掩模。蚀刻优选在具有HF偏置的等离子体蚀刻反应器中进行基座电极和电容VHF偏置花洒。

4. 发明授权

US06614051B1 Device for monitoring substrate charging and method of fabricating same 失效
标题翻译：用于监测基板充电的装置及其制造方法
公开(公告)号：US06614051B1
公开(公告)日：2003-09-02
申请号：US10144056
申请日：2002-05-10
申请人： Shawming Ma
发明人： Shawming Ma
IPC分类号： H01L2358
CPC分类号： H01L22/34
摘要： A charge monitoring device comprising one or more capacitor-resistor pairs. The one or more capacitor-resistor pairs comprise a resistor and a capacitor connected in series. The capacitor comprises a ferroelectric charge storage layer. A method of forming the charge storage device is also provided. The charge monitoring device may be used to measure charge accumulation on a semiconductor wafer. The method comprises the steps of positioning a charge monitoring device in a semiconductor wafer production chamber, initiating a manufacturing process in the chamber and measuring the charge accumulation on the charge monitoring device.
摘要翻译：一种电荷监测装置，包括一个或多个电容器 - 电阻器对。一个或多个电容器 - 电阻器对包括串联连接的电阻器和电容器。电容器包括铁电电荷存储层。还提供了形成电荷存储装置的方法。电荷监测装置可用于测量半导体晶片上的电荷累积。该方法包括以下步骤：将电荷监测装置定位在半导体晶片制造室中，开始在室中的制造过程并测量电荷监测装置上的电荷累积。

5. 发明授权

US6114739A Elevated pin diode active pixel sensor which includes a patterned doped semiconductor electrode 有权
标题翻译：包括图案化掺杂半导体电极的升高的二极管有源像素传感器
公开(公告)号：US6114739A
公开(公告)日：2000-09-05
申请号：US174717
申请日：1998-10-19
申请人： Jeremy A. Theil , Min Cao , Dietrich W. Vook , Frederick A. Perner , Xin Sun , Shawming Ma , Gary W. Ray , Wayne M. Greene , Kit M. Cham , Steven A. Lupi
发明人： Jeremy A. Theil , Min Cao , Dietrich W. Vook , Frederick A. Perner , Xin Sun , Shawming Ma , Gary W. Ray , Wayne M. Greene , Kit M. Cham , Steven A. Lupi
IPC分类号： H01L27/146 , H01L31/02 , H01L27/14 , H01L31/00
CPC分类号： H01L27/14643 , H01L27/14632 , H01L31/02005
摘要： An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. At least one photo sensor is formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode which includes a patterned doped semiconductor layer. An I-layer is formed adjacent to the patterned doped semiconductor layer. A transparent electrode is formed adjacent to the I-layer. A method of forming the active pixel sensor includes forming an interconnect structure over a substrate. Next, a doped semiconductor layer is deposited over the interconnect structure. The doped semiconductor layer is etched forming pixel electrode. An I-layer is deposited over the pixel electrodes. Finally, a transparent conductive layer is deposited over the I-layer.
摘要翻译：有源像素传感器。有源像素传感器包括衬底，与衬底相邻的互连结构以及与互连结构相邻的至少一个光电传感器。在互连结构附近形成至少一个光电传感器。每个光传感器包括包括图案化掺杂半导体层的像素电极。在图案化掺杂半导体层附近形成I层。形成与I层相邻的透明电极。形成有源像素传感器的方法包括在衬底上形成互连结构。接下来，在互连结构上沉积掺杂半导体层。蚀刻形成像素电极的掺杂半导体层。 I层沉积在像素电极上。最后，透明导电层沉积在I层上。

6. 发明授权

US5936261A Elevated image sensor array which includes isolation between the image sensors and a unique interconnection 有权
标题翻译：高分辨率图像传感器阵列，包括图像传感器之间的隔离和独特的互连
公开(公告)号：US5936261A
公开(公告)日：1999-08-10
申请号：US195535
申请日：1998-11-18
申请人： Shawming Ma , Jeremy A. Theil
发明人： Shawming Ma , Jeremy A. Theil
IPC分类号： H01L27/148 , H01L27/146 , H01L31/20
CPC分类号： H01L27/14601
摘要： An image sensor. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. A plurality of image sensors are formed adjacent to the interconnect structure. Each image sensor includes a pixel electrode, and a separate I-layer section formed adjacent to the pixel electrode. The image sensor array further includes an insulating material between each image sensor. A transparent electrode is formed over the image sensors. An inner surface of the transparent electrode is electrically connected to an outer surface of the image sensors and the interconnect.
摘要翻译：图像传感器。图像传感器阵列包括基板。在衬底附近形成互连结构。在互连结构附近形成多个图像传感器。每个图像传感器包括像素电极和与像素电极相邻形成的单独的I层部分。图像传感器阵列还包括每个图像传感器之间的绝缘材料。在图像传感器上形成透明电极。透明电极的内表面与图像传感器和互连件的外表面电连接。

7. 发明授权

US06613666B2 Method of reducing plasma charging damage during dielectric etch process for dual damascene interconnect structures 失效
标题翻译：在双镶嵌互连结构的电介质蚀刻工艺期间减少等离子体充电损伤的方法
公开(公告)号：US06613666B2
公开(公告)日：2003-09-02
申请号：US10013180
申请日：2001-12-07
申请人： Shawming Ma
发明人： Shawming Ma
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76808 , H01L21/76831 , H01L21/76844
摘要： Charging damage, caused by electron shading during plasma etching in a dual damascene structure, is alleviated by first depositing a protective conductive layer which provides a conductive path for maintaining charge balance in the etched structures. This conductive layer reduces the buildup of unbalanced positive charge in the contact opening, and the damage done to underlying layers caused by the resultant tunneling current. Further, if the protective conductive layer comprises a material which can also serve as an interdiffusion barrier layer for the contact opening fill material, a separate subsequent step to deposit such a barrier layer on the contact opening sidewall is avoided. Further, in the process of doing lithography on the trench etch resist layer, the protective conductive layer also functions as an antireflective coating, permitting the stepper to accurately focus the desired pattern.
摘要翻译：通过首先沉积保护导电层来减轻在双镶嵌结构中的等离子体蚀刻期间由电子阴影引起的充电损伤，该保护性导电层提供用于在蚀刻结构中保持电荷平衡的导电路径。该导电层减少了接触开口中不平衡的正电荷的积累以及由所得到的隧道电流引起的对下层的损伤。此外，如果保护性导电层包括也可以用作接触开口填充材料的相互扩散阻挡层的材料，则避免在接触开口侧壁上沉积这种阻挡层的单独的后续步骤。此外，在沟槽蚀刻抗蚀剂层上进行光刻的过程中，保护性导电层还用作抗反射涂层，允许步进器精确地聚焦所需的图案。

8. 发明授权

US06554954B2 Conductive collar surrounding semiconductor workpiece in plasma chamber 有权
公开(公告)号：US06554954B2
公开(公告)日：2003-04-29
申请号：US09827297
申请日：2001-04-03
申请人： Shawming Ma , Ralph H M Straube
发明人： Shawming Ma , Ralph H M Straube
IPC分类号： H01L213065
CPC分类号： H01J37/32697 , H01J2237/0206
摘要： A plasma chamber apparatus and method having a process kit capable of reducing or eliminating electrical arcing from exposed metal at the perimeter of a workpiece. The plasma chamber includes a cathode electrode adjacent the workpiece. A process kit encircles the perimeter of the workpiece. The process kit includes a dielectric shield and an electrically conductive collar that overlies the dielectric shield. The resistivity of the conductive collar is 0.1 ohm-cm or less.

9. 发明授权

US06485988B2 Hydrogen-free contact etch for ferroelectric capacitor formation 有权
标题翻译：用于铁电电容器形成的无氢接触蚀刻
公开(公告)号：US06485988B2
公开(公告)日：2002-11-26
申请号：US09741650
申请日：2000-12-19
申请人： Shawming Ma , Guoqiang Xing , Rahim Kavari , Scott R. Summerfelt , Tomoyuki Sakoda
发明人： Shawming Ma , Guoqiang Xing , Rahim Kavari , Scott R. Summerfelt , Tomoyuki Sakoda
IPC分类号： H01L2100
CPC分类号： H01L21/31122 , H01L21/32136 , H01L21/76838 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/60
摘要： An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.
摘要翻译：本发明的一个实施方案是一种形成导电接触的方法，该导电接触由位于顶部电极下方的底部电极（图4d的304）构成的铁电电容器的顶部电极（图4d的308和310）和铁电材料（图4d的306）位于顶部电极和底部电极之间，该方法包括以下步骤：在顶部电极上形成层（图4的408或312）; 在所述层中形成开口（图4d的414），以通过使用无氢蚀刻剂将所述开口蚀刻到所述层中来暴露所述顶部电极的一部分; 以及将导电材料（图4d的432）沉积在开口中以与顶部电极形成电连接。

10. 发明授权

US06281535B1 Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell 失效
标题翻译：用于非易失性随机存取存储单元的三维铁电电容器结构
公开(公告)号：US06281535B1
公开(公告)日：2001-08-28
申请号：US09236048
申请日：1999-01-22
申请人： Shawming Ma , Gary W. Ray , Florence Eschbach
发明人： Shawming Ma , Gary W. Ray , Florence Eschbach
IPC分类号： H01L2976
CPC分类号： H01L28/60 , H01L21/76838 , H01L27/10811 , H01L27/10855 , H01L27/10888 , H01L28/55 , H01L28/75 , H01L28/82 , H01L28/90
摘要： A capacitor structure or an array of capacitors and a method of fabricating the structure utilize the contours of a cavity created in a layer stack to form two three-dimensional electrode plates. The three-dimensional electrode plates reduce the lateral size of the capacitor structure. The fabrication of the capacitor structure is compatible to conventional CMOS processing technology, in which the resulting capacitor structure may become embedded in a CMOS device. As an example, the capacitor structure may be fabricated along with a MOS transistor to produce a one-transistor-one-capacitor nonvolatile memory cell. Preferably, the three-dimensional electrode plates are made of platinum (Pt) or iridium (Ir) and the capacitor dielectric is a ferrous-electric material, such as lead-zirconate-titanate (PZT) or barium-strontium-titanate (BST). The electrode plates and the capacitor dielectric are formed by depositing layers of appropriate materials within the cavity, which has been formed to include tapering walls in a dielectric layer of the layer stack. Next, portions of the deposited layers, or a “capacitor stack,” are removed down to the surface of the dielectric layer such that only the materials that were deposited within the cavity of the dielectric layer are left. The remaining materials form the electrode plates, as well as the capacitor dielectric. In the preferred embodiment, the selective removal of the capacitor stack portions is accomplished by planarizing the capacitor stack using a Chemical Mechanical Planarization (CMP) process. Alternatively, a sputter etch-back process may be utilized to remove the capacitor stack portions.
摘要翻译：电容器结构或电容器阵列以及制造该结构的方法利用在层叠体中形成的空腔的轮廓以形成两个三维电极板。三维电极板减小了电容器结构的横向尺寸。电容器结构的制造与常规CMOS处理技术兼容，其中所得的电容器结构可能嵌入在CMOS器件中。作为示例，电容器结构可以与MOS晶体管一起制造以产生单晶体管一电容器非易失性存储单元。优选地，三维电极板由铂（Pt）或铱（Ir）制成，并且电容器电介质是诸如锆钛酸铅（PZT）或钛酸锶钡（BST）的亚铁电材料，。电极板和电容器电介质是通过在空腔内沉积适当材料的层而形成的，其已被形成为包括在层堆叠的电介质层中的逐渐变细的壁。接下来，将部分沉积层或“电容器堆叠”去除到电介质层的表面，使得仅留下沉积在介电层的空腔内的材料。剩余的材料形成电极板以及电容器电介质。在优选实施例中，电容器堆叠部分的选择性去除通过使用化学机械平面化（CMP）工艺平坦化电容器堆叠来实现。或者，溅射回蚀工艺可用于去除电容器堆叠部分。

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