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1. 发明申请

US20080290401A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICES WITH CHARGE INJECTION CORNER 有权
标题翻译：带电荷注射角的非线性半导体存储器件
公开(公告)号：US20080290401A1
公开(公告)日：2008-11-27
申请号：US12124143
申请日：2008-05-20
申请人： Kan YASUI , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
发明人： Kan YASUI , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/11526 , H01L27/11546 , H01L29/42344
摘要： An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.
摘要翻译：在存储栅电极上设置有局部集中电场的角部的擦除方法，并且使用Fowler-Nordheim隧道操作将存储栅电极中的电荷注入栅极电介质中的电荷陷阱膜。由于通过Fowler-Nordheim隧道可以减少擦除时的电流消耗，因此可以减少存储器模块的电源电路区域。由于可以提高写入干扰电阻，所以可以通过采用更简单的存储器阵列配置来减少存储器阵列区域。由于这两个效果，可以大大减少存储器模块的面积，从而可以降低制造成本。此外，由于写入和擦除的电荷注入中心彼此一致，所以（编程和擦除）耐久性得到改善。

2. 发明申请

US20080258205A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080258205A1
公开(公告)日：2008-10-23
申请号：US12103697
申请日：2008-04-15
申请人： Tetsuya ISHIMARU , Yasuhiro SHIMAMOTO , Kan YASUI
发明人： Tetsuya ISHIMARU , Yasuhiro SHIMAMOTO , Kan YASUI
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/14 , H01L29/40117 , H01L29/42344 , H01L29/66833
摘要： An erase current of a non-volatile semiconductor memory device is decreased. A memory cell of the non-volatile semiconductor memory device comprises a source region and a drain region formed in a semiconductor substrate. Over a portion of the semiconductor substrate between the source region and the drain region, a select gate electrode is formed via a gate dielectric film. On a side wall of the select gate electrode, a memory gate electrode is formed via a bottom silicon oxide film and a charge-trapping silicon oxynitride film. In the memory cell configured as above, erase operation is performed as follows. By applying a positive voltage to the memory gate electrode, holes are injected from the memory gate electrode into the silicon oxynitride film to decrease a threshold voltage in a program state to a certain level. Thereafter, hot holes generated by a band-to-band tunneling phenomenon are injected into the silicon oxynitride film and the erase operation is completed.
摘要翻译：非易失性半导体存储器件的擦除电流减小。非易失性半导体存储器件的存储单元包括形成在半导体衬底中的源极区域和漏极区域。在源极区域和漏极区域之间的半导体衬底的一部分上，通过栅极电介质膜形成选择栅电极。在选择栅电极的侧壁上，经由底部氧化硅膜和电荷俘获氮氧化硅膜形成存储栅电极。在如上配置的存储单元中，擦除操作如下进行。通过向存储栅电极施加正电压，将空穴从存储栅电极注入到氧氮化硅膜中，以将程序状态的阈值电压降低到一定水平。此后，通过带 - 带隧道现象产生的热孔被注入到氧氮化硅膜中，并且擦除操作完成。

3. 发明申请

US20090050955A1 NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：非挥发性半导体器件及其制造方法
公开(公告)号：US20090050955A1
公开(公告)日：2009-02-26
申请号：US12188412
申请日：2008-08-08
申请人： Kenichi AKITA , Daisuke OKADA , Keisuke KUWAHARA , Yasufumi MORIMOTO , Yasuhiro SHIMAMOTO , Kan YASUI , Tsuyoshi ARIGANE , Tetsuya ISHIMARU
发明人： Kenichi AKITA , Daisuke OKADA , Keisuke KUWAHARA , Yasufumi MORIMOTO , Yasuhiro SHIMAMOTO , Kan YASUI , Tsuyoshi ARIGANE , Tetsuya ISHIMARU
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.
摘要翻译：插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为小于40nm。因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

4. 发明申请

US20090122609A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090122609A1
公开(公告)日：2009-05-14
申请号：US12354867
申请日：2009-01-16
申请人： Tsutomu OKAZAKI , Daisuke OKADA , Kyoya NITTA , Toshihiro TANAKA , Akira KATA , Toshikazu MATSUI , Yasushi ISHII , Digh HISAMOTO , Kan YASUI
发明人： Tsutomu OKAZAKI , Daisuke OKADA , Kyoya NITTA , Toshihiro TANAKA , Akira KATA , Toshikazu MATSUI , Yasushi ISHII , Digh HISAMOTO , Kan YASUI
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

5. 发明申请

US20120086070A1 FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US20120086070A1
公开(公告)日：2012-04-12
申请号：US13328104
申请日：2011-12-16
申请人： Digh HISAMOTO , Shinichiro KIMURA , Kan YASUI , Nozomu MATSUZAKI
发明人： Digh HISAMOTO , Shinichiro KIMURA , Kan YASUI , Nozomu MATSUZAKI
IPC分类号： H01L29/792
CPC分类号： H01L27/11531 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/40117 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

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