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1. 发明授权

US09170776B2 Digital signal processor having instruction set with a logarithm function using reduced look-up table 有权
标题翻译：数字信号处理器具有使用缩减查找表的对数函数的指令集
公开(公告)号：US09170776B2
公开(公告)日：2015-10-27
申请号：US12362899
申请日：2009-01-30
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F1/035 , G06F7/556 , G06F1/03
CPC分类号： G06F7/556 , G06F1/0307 , G06F1/035 , G06F2101/10
摘要： A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table. The disclosed digital signal processor evaluates a logarithm function for an input value, x, by decomposing the input value, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input value, x, and the second part, q, is comprised of a number of bits following the most significant bit, wherein the number is small relative to a number of bits in the input value, x; obtaining a value Log 2 ⁡ ( 1 + 1 2 ⁢ q ) from a first look-up table based on the second part, q; computing an epsilon term, ε, using the expression 2 - N 1 + 1 2 ⁢ q ⁢ r ; evaluating an expression Log2 (1+ε) using a polynomial approximation, such as a cubic approximation; and determining the logarithm function for the input value, x, by summing the values of N, Log Z ⁡ ( 1 + 1 2 ⁢ q ) and Log2(1+ε).
摘要翻译：提供一种数字信号处理器，其具有使用缩减的查找表的具有对数函数的指令集。所公开的数字信号处理器通过将输入值x分解为第一部分N，第二部分q和剩余部分r来评估输入值x的对数函数，其中第一部分N 由输入值x的最高有效位的位置识别，第二部分q由最高有效位之后的位数组成，其中该数目相对于位数输入值x; 基于第二部分从第一查找表获得值Log 2⁡（1 + 1 2 q）q; 使用表达式2-N 1 + 1 2 q r;计算ε项，＆egr; 使用诸如立方近似的多项式近似来评估表达式Log2（1 +＆egr;）; 并且通过将N，Log Z⁡（1 + 1 2 q）和Log2（1 +＆egr））的值求和来确定输入值x的对数函数。

2. 发明申请

US20100138468A1 Digital Signal Processor Having Instruction Set With One Or More Non-Linear Complex Functions 有权
标题翻译：具有一个或多个非线性复合函数的指令集的数字信号处理器
公开(公告)号：US20100138468A1
公开(公告)日：2010-06-03
申请号：US12324926
申请日：2008-11-28
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F7/483 , G06F17/16
CPC分类号： G06F9/3001
摘要： Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel.
摘要翻译：为具有具有一个或多个非线性复合函数的指令集的数字信号处理器提供了方法和装置。为处理器提供了一种方法。从程序获得一个或多个非线性复杂软件指令。非线性复杂软件指令具有至少一个复数作为输入。一个或多个非线性复函数从预定义的指令集应用到至少一个复数。产生由一个复数或两个实数组成的输出。功能单元可以实现一个或多个非线性复合函数。在一个实施例中，公开了一种处理由多个复数组成的复矢量的基于矢量的数字信号处理器。处理器可以并行处理多个复数。

3. 发明授权

US09176735B2 Digital signal processor having instruction set with one or more non-linear complex functions 有权
标题翻译：具有具有一个或多个非线性复合函数的指令集的数字信号处理器
公开(公告)号：US09176735B2
公开(公告)日：2015-11-03
申请号：US12324926
申请日：2008-11-28
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F7/483 , G06F9/30 , G06F17/16
CPC分类号： G06F9/3001
摘要： Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel.
摘要翻译：为具有具有一个或多个非线性复合函数的指令集的数字信号处理器提供了方法和装置。为处理器提供了一种方法。从程序获得一个或多个非线性复杂软件指令。非线性复杂软件指令具有至少一个复数作为输入。一个或多个非线性复函数从预定义的指令集应用到至少一个复数。产生由一个复数或两个实数组成的输出。功能单元可以实现一个或多个非线性复合函数。在一个实施例中，公开了一种处理由多个复数组成的复矢量的基于矢量的数字信号处理器。处理器可以并行处理多个复数。

4. 发明授权

US09128790B2 Digital signal processor having instruction set with an exponential function using reduced look-up table 有权
标题翻译：数字信号处理器具有使用缩减查找表的具有指数函数的指令集
公开(公告)号：US09128790B2
公开(公告)日：2015-09-08
申请号：US12362879
申请日：2009-01-30
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F1/035 , G06F7/556
CPC分类号： G06F7/556 , G06F1/035 , G06F2101/10
摘要： A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q1, larger than a specified value, x0, and a second fractional part, q2, smaller than the specified value, x0; computing 2q2 using a polynomial approximation, such as a cubic approximation; obtaining 2q1 from a look-up table; and evaluating the exponential function for the input value, x, by multiplying 2q2, 2q1 and 2N together. Look-up table entries have a fewer number of bits than a number of bits in the input value, x.
摘要翻译：提供了一种数字信号处理器，其具有使用缩减的查找表的具有指数函数的指令集。所公开的数字信号处理器通过将输入值x分解为整数部分N来估算输入值x的指数函数，N，大于指定值x0的第一小数部分q1，以及第二分数部分，q2，小于指定值x0; 使用多项式近似计算2q2，例如立方近似; 从查表中获得2q1; 并且通过将2q2,2q1和2N相乘来估计输入值x的指数函数。查找表条目具有比输入值x中的位数少的位数。

5. 发明授权

US09069686B2 Digital signal processor having instruction set with one or more non-linear functions using reduced look-up table with exponentially varying step-size 有权
标题翻译：数字信号处理器具有使用具有指数变化的步长的缩小查找表的具有一个或多个非线性函数的指令集
公开(公告)号：US09069686B2
公开(公告)日：2015-06-30
申请号：US12324931
申请日：2008-11-28
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F17/17 , G06F17/10 , G06F1/035 , G06F9/30 , G06F9/38
CPC分类号： G06F17/10 , G06F1/035 , G06F9/3001 , G06F9/383
摘要： A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size and exponentially varying step-sizes. A digital signal processor evaluates a non-linear function for a value, x, by obtaining at least two values from at least one look-up table for the non-linear function that are near the value, x, wherein the at least one look-up table stores a subset of values for the non-linear function using exponentially-varying step sizes; and interpolating the at least two obtained values to obtain a result, y. A position of a leading zero in the value, x, can be used as an index into the at least one look-up table. The interpolation can comprise, for example, a linear interpolation or a polynomial interpolation. A modulo arithmetic operation can optionally be employed for a periodic non-linear function.
摘要翻译：公开了一种数字信号处理器和方法，其具有使用减小尺寸和指数级变化的步长的查找表的具有一个或多个非线性函数的指令集。数字信号处理器通过从近似于值x的非线性函数的至少一个查找表中获得至少两个值来评估值x的非线性函数，其中至少一个外观 -up表使用指数变化的步长存储用于非线性函数的值的子集; 并且内插所述至少两个获得的值以获得结果y。值x中的前导零的位置可以用作至少一个查找表中的索引。内插可以包括例如线性内插或多项式插值。对于周期性非线性函数可以可选地使用模运算。

6. 发明授权

US09069685B2 Digital signal processor having instruction set with one or more non-linear functions using reduced look-up table 有权
标题翻译：具有使用缩减查找表的具有一个或多个非线性函数的指令集的数字信号处理器
公开(公告)号：US09069685B2
公开(公告)日：2015-06-30
申请号：US12324927
申请日：2008-11-28
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F17/17 , G06F17/10 , G06F1/035 , G06F9/30 , G06F9/38
CPC分类号： G06F17/10 , G06F1/035 , G06F9/3001 , G06F9/383
摘要： A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values for the non-linear function that are near the value, x, from at least one look-up table, wherein the at least one look-up table stores a subset of values for the non-linear function; and interpolating the two or more obtained values to obtain a result, y. The interpolation may comprise, for example, a linear interpolation or a polynomial interpolation. In a further variation, a modulo arithmetic operation can be employed for a periodic non-linear function.
摘要翻译：公开了一种使用具有缩小尺寸的查找表的具有一个或多个非线性函数的指令集的数字信号处理器和方法。数字信号处理器通过从至少一个查找表获得接近值x的非线性函数的两个或更多个值来评估值x的非线性函数，其中至少一个查找表存储非线性函数的值的子集; 并且内插两个或更多获得的值以获得结果y。插值可以包括例如线性内插或多项式插值。在另一变型中，可以对周期性非线性函数采用模运算。

7. 发明授权

US09207910B2 Digital signal processor having instruction set with an xK function using reduced look-up table 有权
标题翻译：数字信号处理器具有使用减少的查找表的具有xK功能的指令集
公开(公告)号：US09207910B2
公开(公告)日：2015-12-08
申请号：US12362874
申请日：2009-01-30
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F1/035 , G06F7/556
CPC分类号： G06F7/556 , G06F1/035 , G06F2101/10
摘要： A digital signal processor is provided having an instruction set with an xK function that uses a reduced look-up table. The disclosed digital signal processor evaluates an xK function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the xK function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.
摘要翻译：提供了一种数字信号处理器，其具有使用减少的查找表的具有xK功能的指令集。所公开的数字信号处理器通过在硬件中计算Log（x）来评估输入值x的xK函数; 将Log（x）值乘以K; 以及通过在硬件中对乘法步骤的结果应用指数函数来确定xK函数。 Log（x）和指数函数的计算中的一个或多个使用至少一个查找表，其具有比输入值x中的位数少的位数较少的条目。

8. 发明申请

US20100198894A1 Digital Signal Processor Having Instruction Set With An Exponential Function Using Reduced Look-Up Table 有权
标题翻译：具有使用缩减查找表的指数函数的指令集的数字信号处理器
公开(公告)号：US20100198894A1
公开(公告)日：2010-08-05
申请号：US12362879
申请日：2009-01-30
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F7/52 , G06F7/00 , G06F7/38
CPC分类号： G06F7/556 , G06F1/035 , G06F2101/10
摘要： A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q1, larger than a specified value, x0, and a second fractional part, q2, smaller than the specified value, x0; computing 2q2 using a polynomial approximation, such as a cubic approximation; obtaining 2q1 from a look-up table; and evaluating the exponential function for the input value, x, by multiplying 2q2, 2q1 and 2N together. Look-up table entries have a fewer number of bits than a number of bits in the input value, x.
摘要翻译：提供了一种数字信号处理器，其具有使用缩减的查找表的具有指数函数的指令集。所公开的数字信号处理器通过将输入值x分解为整数部分N来估算输入值x的指数函数，N，大于指定值x0的第一小数部分q1，以及第二分数部分，q2，小于指定值x0; 使用多项式近似计算2q2，例如立方近似; 从查表中获得2q1; 并且通过将2q2,2q1和2N相乘来估计输入值x的指数函数。查找表条目具有比输入值x中的位数少的位数。

9. 发明授权

US09223752B2 Digital signal processor with one or more non-linear functions using factorized polynomial interpolation 有权
标题翻译：具有一个或多个非线性函数的数字信号处理器使用分解多项式插值
公开(公告)号：US09223752B2
公开(公告)日：2015-12-29
申请号：US12324934
申请日：2008-11-28
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F17/17 , G06F17/10 , G06F1/035 , G06F9/30 , G06F9/38
CPC分类号： G06F17/10 , G06F1/035 , G06F9/3001 , G06F9/383
摘要： A digital signal processor and method are disclosed with one or more non-linear functions using factorized polynomial interpolation. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values from at least one look-up table for said non-linear function that are near said value, x; and interpolating said two or more obtained values to obtain a value, y, using a factorized polynomial interpolation.
摘要翻译：公开了使用因式分解多项式插值的一个或多个非线性函数的数字信号处理器和方法。数字信号处理器通过从接近所述值x的所述非线性函数的至少一个查找表中获得两个或更多个值来评估值x的非线性函数; 并且使用因式分解多项式插值来内插所述两个或更多个获得的值以获得值y。

10. 发明申请

US20100198893A1 Digital Signal Processor Having Instruction Set With An Xk Function Using Reduced Look-Up Table 有权
标题翻译：具有使用缩减查找表的Xk函数的指令集的数字信号处理器
公开(公告)号：US20100198893A1
公开(公告)日：2010-08-05
申请号：US12362874
申请日：2009-01-30
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F7/00 , G06F7/52
CPC分类号： G06F7/556 , G06F1/035 , G06F2101/10
摘要： A digital signal processor is provided having an instruction set with an xK function that uses a reduced look-up table. The disclosed digital signal processor evaluates an xK function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the xK function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.
摘要翻译：提供了一种数字信号处理器，其具有使用减少的查找表的具有xK功能的指令集。所公开的数字信号处理器通过在硬件中计算Log（x）来评估输入值x的xK函数; 将Log（x）值乘以K; 以及通过在硬件中对乘法步骤的结果应用指数函数来确定xK函数。 Log（x）和指数函数的计算中的一个或多个使用至少一个查找表，其具有比输入值x中的位数少的位数较少的条目。

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