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1. 发明申请

US20050149744A1 Network processor having cryptographic processing including an authentication buffer 审中-公开
标题翻译：具有加密处理的网络处理器，包括认证缓冲器
公开(公告)号：US20050149744A1
公开(公告)日：2005-07-07
申请号：US10749913
申请日：2003-12-29
申请人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： G06F21/00 , H04L9/32 , H04L29/06
CPC分类号： H04L63/0428 , G06F21/72 , H04L9/32 , H04L63/08
摘要： A network processing having cryptographic processing includes an authentication buffer for storing ciphered data and providing the ciphered data to an authentication core.
摘要翻译：具有加密处理的网络处理包括用于存储加密数据并将加密数据提供给认证核心的认证缓冲器。

2. 发明申请

US20050141715A1 Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor 失效
标题翻译：用于在可编程网络处理器中调度由密码算法核心执行的命令的处理的方法和装置
公开(公告)号：US20050141715A1
公开(公告)日：2005-06-30
申请号：US10747852
申请日：2003-12-29
申请人： Jaroslaw Sydir , Chen-Chi Kuo , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Chen-Chi Kuo , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： H04K1/00
CPC分类号： G06F9/505 , G06F9/5033
摘要： A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.
摘要翻译：一种用于通过网络处理器中的多个加密算法核心调度命令处理的方法和装置。

3. 发明申请

US20050138368A1 Method and apparatus for performing an authentication after cipher operation in a network processor 有权
标题翻译：在网络处理器中进行密码操作之后进行认证的方法和装置
公开(公告)号：US20050138368A1
公开(公告)日：2005-06-23
申请号：US10741676
申请日：2003-12-19
申请人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： H04L9/06 , H04L9/18 , H04L9/32 , H04L29/06 , H04L9/00
CPC分类号： H04L63/0485 , H04L9/0643 , H04L63/12 , H04L2209/125
摘要： A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.
摘要翻译：描述了一种方法和装置，用于通过具有对网络数据分组内的数据进行操作的密码处理核和认证处理核的网络处理器来处理网络数据分组，以便提供网络数据的一次通过加密和认证处理数据包

4. 发明申请

US20060059219A1 Method and apparatus for performing modular exponentiations 审中-公开
标题翻译：用于执行模数乘方的方法和装置
公开(公告)号：US20060059219A1
公开(公告)日：2006-03-16
申请号：US10944353
申请日：2004-09-16
申请人： Kamal Koshy , Gilbert Wolrich , Jaroslaw Sydir , Wajdi Feghali
发明人： Kamal Koshy , Gilbert Wolrich , Jaroslaw Sydir , Wajdi Feghali
IPC分类号： G06F7/38
CPC分类号： G06F7/728
摘要： An arrangement is provided for performing modular exponentiations. A modular exponentiation may be performed by using multiple Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Multiple MMEs of smaller sizes may be chained together to perform modular exponentiations of larger sizes. Additionally, a single MME of a smaller size may be scheduled to perform modular exponentiations of larger sizes. Moreover, the process of performing a Montgomery multiplication may be pipelined both horizontally and vertically. Furthermore, processes of performing two Montgomery multiplications may be interleaved and performed by the same MME or chained MMEs.
摘要翻译：提供了一种用于执行模数乘方的布置。可以通过使用多个蒙哥马利乘法来执行模幂运算。蒙哥马利乘法包括多个基本操作的迭代（例如，进位保存添加），并且由蒙哥马利乘法引擎（MME）执行。较小尺寸的多个MME可以链接在一起以执行较大尺寸的模数乘方。此外，可以调度较小尺寸的单个MME来执行较大尺寸的模数乘方。此外，执行蒙哥马利乘法的过程可以水平和垂直流水线。此外，执行两个蒙哥马利乘法的处理可以由相同的MME或链接的MME进行交织和执行。

5. 发明申请

US20060059220A1 Method and apparatus for performing montgomery multiplications 失效
标题翻译：执行montgomery乘法的方法和装置
公开(公告)号：US20060059220A1
公开(公告)日：2006-03-16
申请号：US10944354
申请日：2004-09-16
申请人： Kamal Koshy , Gilbert Wolrich , Jaroslaw Sydir , Wajdi Feghali
发明人： Kamal Koshy , Gilbert Wolrich , Jaroslaw Sydir , Wajdi Feghali
IPC分类号： G06F7/38
CPC分类号： G06F7/728 , G06F2207/3884
摘要： An arrangement is provided for performing Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Basic operations in each iteration may be performed by multiple Montgomery multiplication processing elements (MMPEs). An MME may be arranged to pipeline the process of performing iterations of multiple basic operations and other operations required to complete a Montgomery multiplication both horizontally and vertically. An MME may also be arranged to interleave processes of performing two Montgomery multiplications.
摘要翻译：提供了执行蒙哥马利乘法的安排。蒙哥马利乘法包括多个基本操作的迭代（例如，进位保存添加），并且由蒙哥马利乘法引擎（MME）执行。每个迭代中的基本操作可以由多个蒙哥马利乘法处理元件（MMPE）执行。 MME可以被布置成管理执行多个基本操作的迭代的过程以及完成水平和垂直的蒙哥马利乘法所需的其他操作。还可以将MME布置成交织执行两个蒙哥马利乘法的处理。

6. 发明申请

US20050149725A1 Method and apparatus for aligning ciphered data 有权
标题翻译：用于对齐加密数据的方法和装置
公开(公告)号：US20050149725A1
公开(公告)日：2005-07-07
申请号：US10749035
申请日：2003-12-30
申请人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： H04L9/00 , H04L29/06
CPC分类号： H04L63/0485 , H04L63/126
摘要： A data processing device includes a crypto unit having an alignment buffer for providing data to transmit buffer elements of a media switch fabric in multiples of a predetermined number of bytes. Ciphered data for a packet can be split over first and second transmit buffer elements so as to reduce the amount of software intervention.
摘要翻译：数据处理装置包括具有对准缓冲器的加密单元，用于以预定数量的字节的倍数提供数据以传送介质交换结构的缓冲器元件。分组的加密数据可以分割在第一和第二发送缓冲器元件上，以便减少软件干预的量。

7. 发明申请

US20140095845A1 APPARATUS AND METHOD FOR EFFICIENTLY EXECUTING BOOLEAN FUNCTIONS 审中-公开
标题翻译：有效执行布尔函数的装置和方法
公开(公告)号：US20140095845A1
公开(公告)日：2014-04-03
申请号：US13631807
申请日：2012-09-28
申请人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Kirk Yap
发明人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Kirk Yap
IPC分类号： G06F9/30
摘要： An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.
摘要翻译：描述了一种用于在流水线处理器中执行有效的布尔运算的装置和方法，其在一个实施例中不本地支持三个操作数指令。例如，根据本发明的一个实施例的处理器包括：一组用于存储打包操作数的寄存器; 用于执行单个指令的布尔运算逻辑，其使用打包在该组寄存器中的三个或更多个源操作数，布尔运算逻辑读取至少三个源操作数，并且立即值对三个源操作数执行布尔运算，其中，布尔操作包括：组合从三个操作数中的每一个读取的位以形成立即值的索引，该索引标识立即值内的位位置; 从识别的位置读取该位从立即值; 并将来自所识别的立即值的比特位置的比特存储在目的地寄存器中。

8. 发明申请

US20100153829A1 RESIDUE GENERATION 失效
标题翻译：残留生成
公开(公告)号：US20100153829A1
公开(公告)日：2010-06-17
申请号：US12336029
申请日：2008-12-16
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
IPC分类号： H03M13/09 , G06F7/72 , G06F11/10
CPC分类号： G06F7/724 , H03M13/091
摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.
摘要翻译：在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少是乘法的结果。所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。

9. 发明授权

US08189792B2 Method and apparatus for performing cryptographic operations 有权
标题翻译：用于执行加密操作的方法和装置
公开(公告)号：US08189792B2
公开(公告)日：2012-05-29
申请号：US12005680
申请日：2007-12-28
申请人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
发明人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
IPC分类号： G06F21/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路加密算法宽度（或更小）的宽度。可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。描述和要求保护其他实施例。

10. 发明授权

US08042025B2 Determining a message residue 有权
标题翻译：确定消息残差
公开(公告)号：US08042025B2
公开(公告)日：2011-10-18
申请号：US12291621
申请日：2008-11-12
申请人： Vinodh Gopal , Gilbert Wolrich , Wajdi Feghali , Erdinc Ozturk , Shay Gueron
发明人： Vinodh Gopal , Gilbert Wolrich , Wajdi Feghali , Erdinc Ozturk , Shay Gueron
IPC分类号： H03M13/03
CPC分类号： G06F7/724 , H03M13/091
摘要： In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.
摘要翻译：在一个方面，用于确定相对于包括一系列段的消息的多项式的模块余数的电路。在另一方面，访问具有第一末端格式的第一号码的至少一部分的电路基于具有与第一末端格式相反的端格式的第三号码的位反射和位移来确定第二号码，以及执行第一数字和第一数字的至少一部分的多项式相乘。

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