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1. 发明授权

US08176453B2 Power-aware debugging 有权
标题翻译：电源感知调试
公开(公告)号：US08176453B2
公开(公告)日：2012-05-08
申请号：US12558259
申请日：2009-09-11
申请人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu , Jun Zhao
发明人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu , Jun Zhao
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
摘要翻译：调试系统根据IC设计和基于IC设计的IC行为的逻辑仿真结果生成显示器。该IC设计包括描述IC的IC的硬件描述语言（HDL）模型，其包括经由数据信号进行通信的小区实例和用于向小区实例供电的电源。 IC设计还包括描述IC设计的功率意图的功率定义标记语言（PDML）模型。调试系统产生表示HDL代码的显示器，其被注释以指示由PDML模型描述的IC设计的功率意图与由显示器表示的HDL模型的部分有关。调试系统还生成信号跟踪显示，指示IC设计的逻辑和电源意图如何在逻辑模拟期间在用户选择的时间影响用户选择的信号的值。

2. 发明申请

US20100192115A1 POWER-AWARE DEBUGGING 有权
标题翻译：功率检测
公开(公告)号：US20100192115A1
公开(公告)日：2010-07-29
申请号：US12558259
申请日：2009-09-11
申请人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu
发明人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
摘要翻译：调试系统根据IC设计和基于IC设计的IC行为的逻辑仿真结果生成显示器。该IC设计包括描述IC的IC的硬件描述语言（HDL）模型，其包括经由数据信号进行通信的小区实例和用于向小区实例供电的电源。 IC设计还包括描述IC设计的功率意图的功率定义标记语言（PDML）模型。调试系统产生表示HDL代码的显示器，其被注释以指示由PDML模型描述的IC设计的功率意图与由显示器表示的HDL模型的部分有关。调试系统还生成信号跟踪显示，指示IC设计的逻辑和电源意图如何在逻辑模拟期间在用户选择的时间影响用户选择的信号的值。

3. 发明授权

US11085421B2 Planet carrier of a wind turbine gearbox with improved lubricant path 有权
公开(公告)号：US11085421B2
公开(公告)日：2021-08-10
申请号：US16635817
申请日：2017-08-03
申请人： General Electric Company , Kai Yang , Claus Kruempelbeck , Wei Zheng , Rong Li
发明人： Kai Yang , Claus Kruempelbeck , Wei Zheng , Rong Li
IPC分类号： F03D80/70 , F03D15/00 , F16H57/08 , F16H57/02
摘要： A gearbox assembly includes a gearbox housing and a planetary gear system configured within the gearbox housing. The planetary gear system includes a plurality of planet gears, at least one sun gear, at least one ring gear, at least one planetary carrier operatively coupled with the plurality of planet gears, and a plurality of pin shafts. Each of the plurality of planet gears are arranged so as to rotate around one of the plurality of pin shafts. Further, the plurality of planet gears are engaged with the ring gear and configured to rotate about the sun gear. The gearbox assembly also includes a first lubricant path defined from a first location to a second location through the at least one planetary carrier. Moreover, the first lubricant path is located outside of the plurality of pin shafts.

4. 发明授权

US09681455B2 Methods for reducing interference in a communication system 有权
公开(公告)号：US09681455B2
公开(公告)日：2017-06-13
申请号：US13010262
申请日：2011-01-20
申请人： Kai Yang , Chan-Byoung Chae , Doru Calin , Denis Rouffet , Simon Yiu
发明人： Kai Yang , Chan-Byoung Chae , Doru Calin , Denis Rouffet , Simon Yiu
IPC分类号： H04B1/00 , H04W72/08 , H04B7/0408 , H04W16/28 , H04W16/30 , H04W72/04
CPC分类号： H04W72/082 , H04B7/0408 , H04W16/28 , H04W16/30 , H04W72/046
摘要： Example embodiments are directed to methods of reducing interference in a communication system. In at least one example embodiment, a method includes first determining, by a first transmitter having a multi-directional antenna configured to produce a plurality of beams, at least one interference level of at least one interfering beam of a plurality of beams of at least one transmitter in the communication system, second determining a transmitting beam pattern based on the interference level, the transmitting beam pattern indicating a sequence of illuminating the plurality of beams at corresponding time slots, third determining a fractional frequency reuse pattern based on the transmitting beam pattern, and transmitting data based on the transmitting beam pattern and the frequency reuse pattern.

5. 发明授权

US08743967B2 Multi-format video decoder with vector processing instructions and methods for use therewith 有权
标题翻译：具有向量处理指令的多格式视频解码器和与其一起使用的方法
公开(公告)号：US08743967B2
公开(公告)日：2014-06-03
申请号：US13076554
申请日：2011-03-31
申请人： Indra Laksono , Kai Yang , Hongri Wang , Dong Liu , Xu Gang (Wilf) Zhao , Eric Young , Edward Hong
发明人： Indra Laksono , Kai Yang , Hongri Wang , Dong Liu , Xu Gang (Wilf) Zhao , Eric Young , Edward Hong
IPC分类号： H04N7/12 , H04N7/50
CPC分类号： H04N19/103 , H04N19/136 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/91
摘要： A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.
摘要翻译：视频解码器包括从编码视频信号产生熵解码（EDC）数据的熵解码装置。多格式视频解码装置包括从EDC数据生成解码视频信号的多个矢量处理器单元。多个向量处理单元通过格式化为包括向量指令部分，标量指令部分和分支指令部分的VPU指令来编程。

6. 发明授权

US08359559B2 Methods and systems for evaluating checker quality of a verification environment 有权
标题翻译：用于评估验证环境的检验质量的方法和系统
公开(公告)号：US08359559B2
公开(公告)日：2013-01-22
申请号：US12977376
申请日：2010-12-23
申请人： Kai Yang , Michael Lyons , Kuo-Ching Lin , Wei-Ting Tu , Chih-Wen Chang , Tein-Chun Wei
发明人： Kai Yang , Michael Lyons , Kuo-Ching Lin , Wei-Ting Tu , Chih-Wen Chang , Tein-Chun Wei
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022 , G06F17/504 , G06F2217/10
摘要： Methods and systems for evaluating checker quality of a verification environment are provided. In some embodiments, an overall sensitivity for the verification environment and an individual sensitivity for a respective checker are calculated. The overall sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to a checker system including at least one checker, can be detected by the verification environment. The individual sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to at least one specific probe among a plurality of probes of a design, can be detected by the checker corresponding to the specific probe. The overall checker sensitivity numbers can show the robustness of the check system. The individual checker sensitivity can guide the user which individual checker or checkers to improve.
摘要翻译：提供了用于评估验证环境的检查器质量的方法和系统。在一些实施例中，计算验证环境的总体灵敏度和相应检查器的个体灵敏度。总体灵敏度是通过验证环境可以检测到传播到包括至少一个检验器的检查系统的多个有问题的设计行为的概率。个体敏感度是通过与特定探针对应的检查器可以检测到在设计的多个探针中传播到至少一个特定探针的多个有问题的设计行为的概率。整体检查灵敏度数字可以显示检查系统的稳健性。单独的检查灵敏度可以指导用户哪个单独的检查器或检查器改进。

7. 发明申请

US20120230427A1 MULTI-FORMAT VIDEO DECODER WITH FILTER VECTOR PROCESSING AND METHODS FOR USE THEREWITH 有权
标题翻译：具有滤波器矢量处理的多格式视频解码器及其使用方法
公开(公告)号：US20120230427A1
公开(公告)日：2012-09-13
申请号：US13076568
申请日：2011-03-31
申请人： Edward Hong , Dong Liu , Hongri Wang , Kai Yang
发明人： Edward Hong , Dong Liu , Hongri Wang , Kai Yang
IPC分类号： H04N7/26
CPC分类号： H04N19/103 , H04N19/136 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/91
摘要： A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units includes at least one filter vector processor that operates in conjunction with a plurality of programmable filter parameters.
摘要翻译：视频解码器包括从编码视频信号产生熵解码（EDC）数据的熵解码装置。多格式视频解码装置包括从EDC数据生成解码视频信号的多个矢量处理器单元。多个矢量处理单元包括至少一个与多个可编程滤波器参数相结合的滤波器矢量处理器。

8. 发明申请

US20090232074A1 AUCTION BASED RESOURCE ALLOCATION IN WIRELESS SYSTEMS 有权
标题翻译：无线系统中基于拍卖的资源分配
公开(公告)号：US20090232074A1
公开(公告)日：2009-09-17
申请号：US12399769
申请日：2009-03-06
申请人： Kai Yang , Narayan Prasad , Xiaodong Wang
发明人： Kai Yang , Narayan Prasad , Xiaodong Wang
IPC分类号： H04W72/04 , H04L27/28
CPC分类号： H04L5/0007 , H04L5/0032 , H04L5/0037 , H04L5/0046 , H04W52/243 , H04W52/262 , H04W52/267 , H04W52/346 , H04W72/1257
摘要： Systems and methods to assign one or more resources in a multi-user cellular Orthogonal Frequency-Division Multiple Access (OFDMA) uplink includes specifying a resource allocation problem for one or more resources; converting the resource allocation problem into an assignment problem; solving the assignment problem through an auction; and allocating one or more resources to cellular users to maximize a system utility.
摘要翻译：在多用户蜂窝正交频分多址（OFDMA）上行链路中分配一个或多个资源的系统和方法包括：为一个或多个资源指定资源分配问题; 将资源分配问题转化为分配问题; 通过拍卖解决作业问题; 并将一个或多个资源分配给蜂窝用户以最大化系统效用。

9. 发明申请

US20090223070A1 Cutting machine 有权
标题翻译：切割机
公开(公告)号：US20090223070A1
公开(公告)日：2009-09-10
申请号：US12379996
申请日：2009-03-05
申请人： Kai Yang , Kenji Abe
发明人： Kai Yang , Kenji Abe
IPC分类号： B27B9/00
CPC分类号： B23D59/006
摘要： It is, accordingly, an object of the present invention to provide a technique which is effective in preventing chips generated during cutting operation on a workpiece from being accumulated in a region ahead in a cutting direction. A representative cutting machine includes a motor, a blade, a body housing having a first region that houses the motor and a second region that covers the blade and projects forward of a front surface of the first region, a base, an angular plate, an outlet formed in the body housing, an opening and a blocking part. The blocking part prevents the air discharged from the outlet from flowing out laterally with respect to the moving direction of the base through a clearance between a front end of the second region and the one end of the angular plate and thereby helps the air discharged from the outlet flow into the opening.
摘要翻译：因此，本发明的目的是提供一种技术，其有效地防止在切割操作期间在工件上产生的碎屑积聚在切割方向上的区域中。代表性的切割机包括马达，叶片，具有容纳马达的第一区域的主体壳体和覆盖叶片并在第一区域的前表面向前突出的第二区域，基座，角板，出口形成在主体壳体中，一个开口和一个阻挡部分。阻挡部防止从出口排出的空气相对于基座的移动方向横向流过第二区域的前端和角板的一端之间的间隙，从而有助于从出口流入开口。

10. 发明授权

US07132363B2 Stabilizing fluorine etching of low-k materials 失效
标题翻译：稳定低k材料的氟蚀刻
公开(公告)号：US07132363B2
公开(公告)日：2006-11-07
申请号：US09817056
申请日：2001-03-27
申请人： Kai Yang , Darrell M. Erb , Fei Wang
发明人： Kai Yang , Darrell M. Erb , Fei Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： Damascene processing is implemented with dielectric barrier films (50, 90, 91) for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films (50, 31) to avoid misalignment problems. Embodiments further include dual damascene (100A, 100B) processing using Cu metallization (100).
摘要翻译：用电介质阻挡膜（50,90,91）实现镶嵌加工，以改善台阶覆盖和降低的接触电阻。实施例包括使用两种不同的介电膜（50,31）来避免不对准问题。实施例还包括使用Cu金属化（100）的双镶嵌（100A，100B）处理。

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