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1. 发明申请

US20120157769A1 CAPSULE ENDOSCOPE 审中-公开
标题翻译：胶囊内窥镜
公开(公告)号：US20120157769A1
公开(公告)日：2012-06-21
申请号：US13329293
申请日：2011-12-18
申请人： Peng Fei Zhu , Yong Qiang Wu , Kai Feng Wang , Hong Xia Sun
发明人： Peng Fei Zhu , Yong Qiang Wu , Kai Feng Wang , Hong Xia Sun
IPC分类号： A61B1/04
CPC分类号： G01C19/02 , A61B1/00016 , A61B1/0002 , A61B1/00032 , A61B1/00057 , A61B1/00158 , A61B1/041 , A61B1/0661 , G01C19/00
摘要： An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.
摘要翻译：实施例包括具有图像轴的图像捕获装置和可操作以指示图像轴的取向的陀螺仪的装置。胶囊内窥镜系统的实施例包括成像胶囊和外部单元。成像胶囊可以包括具有图像轴的图像捕获装置和可操作以指示图像轴的取向的陀螺仪。外部单元可以包括陀螺仪，其可操作以指示受试者的方位和由受试者佩戴的线束并可操作以将陀螺仪与对象对准。成像胶囊可以发送和图像到外部单元进行处理和显示，并且外部单元可以提供相对于身体的图像轴取向的计算。

2. 发明申请

US20120173846A1 METHOD TO REDUCE THE ENERGY COST OF NETWORK-ON-CHIP SYSTEMS 审中-公开
标题翻译：降低网络中芯片系统能源成本的方法
公开(公告)号：US20120173846A1
公开(公告)日：2012-07-05
申请号：US13325614
申请日：2011-12-14
申请人： Kai Feng Wang , Peng Fei Zhu , Hong Xia Sun , Yong Qiang Wu
发明人： Kai Feng Wang , Peng Fei Zhu , Hong Xia Sun , Yong Qiang Wu
IPC分类号： G06F15/76 , G06F9/22
CPC分类号： G06F1/32
摘要： In a network-on-chip (NoC) system, multiple data messages may be transferred among modules of the system. Power consumption due to the transfer of the messages may affect a cost and overall performance of the system. A described technique provides a way to reduce a volume of data transferred in the NoC system by exploiting redundancy of data messages. Thus, if a data message to be sent from a source in the NoC includes so-called “zero” bytes that are bytes including only bits set to “0,” such zero bytes may not be transmitted in the NoC. Information on whether each byte of the data message is a zero byte may be recorded in a storage such as a data structure. This information, together with non-zero bytes of the data message, may form a compressed version of the data message. The information may then be used to uncompress the compressed data message at a destination.
摘要翻译：在片上网络（NoC）系统中，可以在系统的模块之间传送多个数据消息。由于消息传送引起的功耗可能会影响系统的成本和整体性能。所描述的技术提供了一种通过利用数据消息的冗余来减少在NoC系统中传送的数据量的方法。因此，如果要从NoC中的源发送的数据消息包括仅包括设置为“0”的字节的所谓的“零”字节，那么这种零字节可能不会在NoC中发送。关于数据消息的每个字节是否为零字节的信息可以被记录在诸如数据结构的存储器中。该信息与数据消息的非零字节可以形成数据消息的压缩版本。然后可以使用该信息来在目的地解压缩压缩数据消息。

3. 发明授权

US08583901B2 Register renaming system using multi-bank physical register mapping table and method thereof 有权
标题翻译：使用多库物理寄存器映射表及其方法的注册重命名系统
公开(公告)号：US08583901B2
公开(公告)日：2013-11-12
申请号：US12700638
申请日：2010-02-04
申请人： Peng Fei Zhu , Hong-Xia Sun , Yong Qiang Wu
发明人： Peng Fei Zhu , Hong-Xia Sun , Yong Qiang Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/384
摘要： Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.
摘要翻译：提供了利用多库实现物理寄存器映射表的处理器架构的实施例。将结构寄存器与物理寄存器相关联的寄存器重命名系统包括物理寄存器映射表和重命名逻辑。物理寄存器映射表具有多个表示每个物理寄存器的状态的条目。映射表具有多个非重叠部分，每个部分具有映射表的相应条目。重命名逻辑被耦合以并行地搜索映射表的多个部分以识别指示相应物理寄存器具有第一状态的条目。重命名逻辑选择性地将多个体系结构寄存器中的每一个相关于被识别为处于第一状态的相应物理寄存器。还提供了利用多库实现物理寄存器映射表的方法。

4. 发明申请

US20100205409A1 NOVEL REGISTER RENAMING SYSTEM USING MULTI-BANK PHYSICAL REGISTER MAPPING TABLE AND METHOD THEREOF 有权
标题翻译：使用多银行物理寄存器映射表的新型寄存器恢复系统及其方法
公开(公告)号：US20100205409A1
公开(公告)日：2010-08-12
申请号：US12700638
申请日：2010-02-04
申请人： Peng Fei Zhu , Hong-Xia Sun , Yong Qiang Wu
发明人： Peng Fei Zhu , Hong-Xia Sun , Yong Qiang Wu
IPC分类号： G06F9/30 , G06F1/04
CPC分类号： G06F9/3012 , G06F9/384
摘要： Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.
摘要翻译：提供了利用多库实现物理寄存器映射表的处理器架构的实施例。将结构寄存器与物理寄存器相关联的寄存器重命名系统包括物理寄存器映射表和重命名逻辑。物理寄存器映射表具有多个表示每个物理寄存器的状态的条目。映射表具有多个非重叠部分，每个部分具有映射表的相应条目。重命名逻辑被耦合以并行地搜索映射表的多个部分以识别指示相应物理寄存器具有第一状态的条目。重命名逻辑选择性地将多个体系结构寄存器中的每一个相关于被识别为处于第一状态的相应物理寄存器。还提供了利用多库实现物理寄存器映射表的方法。

5. 发明授权

US09015450B2 Apparatus utilizing efficient hardware implementation of shadow registers and method thereof 有权
标题翻译：利用影子寄存器的高效硬件实现的装置及其方法
公开(公告)号：US09015450B2
公开(公告)日：2015-04-21
申请号：US12690719
申请日：2010-01-20
申请人： Hong-Xia Sun , Peng Fei Zhu , Yong Qiang Wu
发明人： Hong-Xia Sun , Peng Fei Zhu , Yong Qiang Wu
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/30116 , G06F9/30123 , G06F9/384 , G06F9/3863
摘要： Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.
摘要翻译：处理器架构的实施例在硬件中有效地实现影子寄存器。处理器中的寄存器系统包括耦合到寄存器重命名逻辑的一组物理数据寄存器。当处理器处于第一处理器状态时，寄存器重命名逻辑将数据存储在物理寄存器组中并从中检索数据。寄存器重命名逻辑将具有第一操作状态的一组物理寄存器中的一个标识为第一组寄存器，并且响应于处理器的指示，将该组物理寄存器中剩余的一组物理寄存器识别为第二组寄存器从第一处理器状态进入第二处理器状态。当处理器处于第二处理器状态时，寄存器重命名逻辑将数据存储在第二组寄存器中，而不是第一组寄存器中的数据。

6. 发明申请

US20100205387A1 APPARATUS UTILIZING EFFICIENT HARDWARE IMPLEMENTATION OF SHADOW REGISTERS AND METHOD THEREOF 有权
标题翻译：利用有效的硬件实现方法的设备及其方法
公开(公告)号：US20100205387A1
公开(公告)日：2010-08-12
申请号：US12690719
申请日：2010-01-20
申请人： Hong-Xia Sun , Peng Fei Zhu , Yong Qiang Wu
发明人： Hong-Xia Sun , Peng Fei Zhu , Yong Qiang Wu
IPC分类号： G06F12/00
CPC分类号： G06F9/30116 , G06F9/30123 , G06F9/384 , G06F9/3863
摘要： Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.
摘要翻译：处理器架构的实施例在硬件中有效地实现影子寄存器。处理器中的寄存器系统包括耦合到寄存器重命名逻辑的一组物理数据寄存器。当处理器处于第一处理器状态时，寄存器重命名逻辑将数据存储在物理寄存器组中并从中检索数据。寄存器重命名逻辑将具有第一操作状态的一组物理寄存器中的一个标识为第一组寄存器，并且响应于处理器的指示，将该组物理寄存器中的剩余的一组标识为第二组寄存器从第一处理器状态进入第二处理器状态。当处理器处于第二处理器状态时，寄存器重命名逻辑将数据存储在第二组寄存器中，而不是第一组寄存器中的数据。

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