专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20200089426A1 MANAGEMENT DEVICE, INFORMATION PROCESSING APPARATUS, AND MEMORY CONTROL METHOD 审中-公开
公开(公告)号：US20200089426A1
公开(公告)日：2020-03-19
申请号：US16287027
申请日：2019-02-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yusuke SHIROTA , Tatsunori KANAI
IPC分类号： G06F3/06
摘要： According to an embodiment, a management device is for controlling readout and writing of data that are performed by a processing circuit with respect to a non-volatile memory storing a plurality of pages. The non-volatile memory includes a high-temperature region and a low-temperature region in which temperature is relatively lower than in the high-temperature region during operation. The management device includes one or more processors configured to move storage positions of the plurality of pages in such a manner that pages included in a high access page group are stored more in the low-temperature region than in the high-temperature region in the voluntary memory, where the plurality of pages are classified into the high access page group in which access amounts are relatively high, and a low access page group in which access amounts are relatively low.

2. 发明申请

US20190294355A1 INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, ESTIMATION DEVICE, ESTIMATION METHOD, AND COMPUTER PROGRAM PRODUCT 审中-公开
公开(公告)号：US20190294355A1
公开(公告)日：2019-09-26
申请号：US16117315
申请日：2018-08-30
申请人： Kabushiki Kaisha Toshiba
发明人： Yusuke SHIROTA , Mayuko KOEZUKA , Tatsunori KANAI
IPC分类号： G06F3/06
摘要： An information processing device according to an embodiment includes a processing circuit. The processing circuit is configured to: obtains operation information; estimates, based on the obtained operation information, the execution performance of memory accesses with respect to a first memory and a nonvolatile memory unit in the case in which a managing device performs operations according to each of a plurality of memory control methods; selects, based on the execution performance estimated for each memory control method, any one memory control method from among a plurality of memory control methods; and performs a setting operation with respect to an access managing unit in such a way that the managing device accesses the first memory and the nonvolatile memory unit according to the selected memory control method.

3. 发明申请

US20200081634A1 INFORMATION PROCESSING APPARATUS, MEMORY CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT 审中-公开
公开(公告)号：US20200081634A1
公开(公告)日：2020-03-12
申请号：US16286786
申请日：2019-02-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tatsunori KANAI , Yusuke SHIROTA
IPC分类号： G06F3/06
摘要： An information processing apparatus according to an embodiment includes a first memory, a non-volatile memory, and one or more processors. The processor is configured to execute information processing on data stored in those memories. The processor allocates, to each of pages included in a file stored in the non-volatile memory by executing an operating system, a memory access method that indicates either copy access processing or direct access processing to be executed. The copy access processing performs writing and readout of data copied from the non-volatile memory into the first memory. The direct access processing directly performs writing and readout of data stored in the non-volatile memory. The processor accesses those memories by the memory access method allocated to each of the pages included in the file when the operating system receives a request from an application program for writing or readout on the file.

4. 发明申请

US20190286368A1 MANAGEMENT DEVICE AND INFORMATION PROCESSING DEVICE 审中-公开
公开(公告)号：US20190286368A1
公开(公告)日：2019-09-19
申请号：US16117806
申请日：2018-08-30
申请人： Kabushiki Kaisha Toshiba
发明人： Yusuke SHIROTA , Tatsunori KANAI
IPC分类号： G06F3/06
摘要： A management device is configured to control reading and writing of data as performed by a processing circuit with respect to a nonvolatile memory. The management device includes circuitry configured to: in response to a request from the processing circuit, perform writing or reading with respect to the nonvolatile memory; in response to writing with respect to the nonvolatile memory, update a table indicating a rewriting count for each area in the nonvolatile memory; detect writing having a high degree of locality representing rewriting operation performed to an extent equal to or greater than a reference value, with respect to the same area in the nonvolatile memory by refer to the table; and identify an area under attack in which the writing having the high degree of locality is performed.

5. 发明申请

US20180253374A1 MANAGEMENT DEVICE, INFORMATION PROCESSING DEVICE, AND MANAGEMENT METHOD 审中-公开
公开(公告)号：US20180253374A1
公开(公告)日：2018-09-06
申请号：US15689009
申请日：2017-08-29
申请人： Kabushiki Kaisha Toshiba
发明人： Shiyo YOSHIMURA , Tatsunori KANAI , Yusuke SHIROTA , Satoshi SHIRAI
IPC分类号： G06F12/02 , G06F3/06
摘要： According to an embodiment, a management device includes a counter storage unit, a first management information storage unit, and an update unit. The first management information storage unit stores a first management table capable of storing first management information about each of a predetermined number of first areas. The first management information indicates whether each second area included in a corresponding first area has data written therein. In response to writing of first data into the nonvolatile memory, when a state of a target second area indicated in the first management information about a target first area is an unwritten state, the update unit changes the state of the target second area to a written state; while when the state of the target second area indicated in the first management information is the written state, the update unit updates the counter value for the target first area.

6. 发明申请

US20170228155A1 INFORMATION PROCESSING APPARATUS, STORAGE DEVICE, AND COMPUTER PROGRAM PRODUCT 审中-公开
公开(公告)号：US20170228155A1
公开(公告)日：2017-08-10
申请号：US15422894
申请日：2017-02-02
申请人： Kabushiki Kaisha Toshiba
发明人： Yusuke SHIROTA , Tatsunori KANAI , Shiyo YOSHIMURA
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0659 , G06F3/0688
摘要： According to an embodiment, an information processing apparatus includes a processing device, a first memory, and a second memory. The processing device executes first processing on first data. The second memory stores the first data and has a data access latency higher than that of the first memory. The first data includes first and second pages, the first page being read/written times not less than a threshold in a certain period shorter than a period for executing the first processing, the second page being read/written times less than the threshold in the certain period. The processing device includes a controller configured to execute first access to move the first page to the first memory and then read/write data from/to the moved first page, and execute second access to directly read/write data from/to the second page of the second memory.

7. 发明申请

US20190294989A1 MODEL GENERATION APPARATUS, INFORMATION PROCESSING APPARATUS, MODEL GENERATION METHOD, AND COMPUTER PROGRAM PRODUCT 审中-公开
公开(公告)号：US20190294989A1
公开(公告)日：2019-09-26
申请号：US16117339
申请日：2018-08-30
申请人： Kabushiki Kaisha Toshiba
发明人： Mayuko KOEZUKA , Yusuke SHIROTA , Tatsunori KANAI
IPC分类号： G06N7/00 , G06F11/34 , G06F11/30
摘要： A model generation apparatus according to an embodiment includes a processor circuit. The processor circuit is configured to: divide time-series data of operation information in a time direction to generate a plurality of segments; allocate any one memory control method of a plurality of memory control methods to each of the plurality of segments; estimate, for each of the plurality of segments, execution performance of memory access that is obtainable in a case where an information processing apparatus executes processing of a corresponding segment by an allocated memory control method; select a plurality of training segments from among the plurality of segments; and generate a decision model based on the selected plurality of training segments.

8. 发明申请

US20190286347A1 MANAGEMENT APPARATUS, INFORMATION PROCESSING APPARATUS, MANAGEMENT METHOD, AND COMPUTER PROGRAM PRODUCT 审中-公开
公开(公告)号：US20190286347A1
公开(公告)日：2019-09-19
申请号：US16121337
申请日：2018-09-04
申请人： Kabushiki Kaisha Toshiba
发明人： Tatsunori KANAI , Yusuke SHIROTA
IPC分类号： G06F3/06
摘要： According to an embodiment, a management apparatus manages access to a plurality of types of storage units by a processing circuit. Each of the plurality of types of storage units includes a plurality of first regions, and each of the plurality of first regions includes a plurality of second regions. The management apparatus includes a circuitry configured to function as a management unit. The management unit manages a management table in which identification information of one or more of the plurality of first regions and access management information defining access information indicating whether or not each second region included in the one or more of the plurality of first regions is accessed by the processing circuit are associated with each other.

9. 发明申请

US20170228012A1 INFORMATION PROCESSING APPARATUS AND COMPUTER PROGRAM PRODUCT 审中-公开
公开(公告)号：US20170228012A1
公开(公告)日：2017-08-10
申请号：US15419044
申请日：2017-01-30
申请人： Kabushiki Kaisha Toshiba
发明人： Yusuke SHIROTA , Tatsunori KANAI , Shiyo YOSHIMURA , Satoshi SHIRAI
IPC分类号： G06F1/32 , G06F1/08
CPC分类号： G06F1/3275 , G06F1/08 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F3/0625 , G06F3/0644 , G06F3/0646 , Y02D10/126 , Y02D10/14 , Y02D10/24
摘要： According to an embodiment, an information processing apparatus includes a processing device, a first memory, a second memory, and a controller. The processing device is configured to process first data. The first memory is configured to store at least part of the first data and has an active region supplied with power necessary for holding data. The second memory is configured to store part of the first data. The controller is configured to change number of active regions such that processing information is not more than a threshold. The processing information indicates an amount of processing for moving at least part of second data stored in the first memory to the second memory and for moving at least part of third data stored in the second memory to the first memory, in a certain period for processing the first data having a size larger than active regions.

10. 发明申请

US20150058588A1 SEMICONDUCTOR DEVICE AND MEMORY PROTECTION METHOD 有权
标题翻译：半导体器件和存储器保护方法
公开(公告)号：US20150058588A1
公开(公告)日：2015-02-26
申请号：US14509091
申请日：2014-10-08
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroto NAKAI , Kenichi MAEDA , Tatsunori KANAI
IPC分类号： G06F9/52
CPC分类号： G06F9/524 , G06F9/544 , G06F12/0246
摘要： According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.
摘要翻译：根据一个实施例，半导体器件包括处理器和存储器件。存储器件具有非易失性半导体存储器件，并且被配置为用作处理器的主存储器。当处理器执行多个程序时，处理器管理作为各个程序的工作流程执行程序所需的信息，并创建表，其保持各工作组所需的信息和各条信息的地址之间的关系在存储器件中，用于各个工作台。处理器参考相应工作台的相应表访问存储器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式