专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09418960B2 Semiconductor chip and semiconductor package 有权
标题翻译：半导体芯片和半导体封装
公开(公告)号：US09418960B2
公开(公告)日：2016-08-16
申请号：US14634571
申请日：2015-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Shohei Fukuda
IPC分类号： H01L29/40 , H01L23/00 , H01L23/48 , H01L23/528 , H03K19/177 , G06F17/50 , H03K19/0185
CPC分类号： H01L24/49 , G06F17/5068 , H01L23/481 , H01L23/528 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/05554 , H01L2224/06133 , H01L2224/06135 , H01L2224/06139 , H01L2224/48011 , H01L2224/48091 , H01L2224/49431 , H01L2224/49433 , H01L2924/00014 , H01L2924/386 , H03K19/018514 , H03K19/17744 , H01L2224/45099 , H01L2224/05599
摘要： The driver semiconductor package includes a base substrate. The semiconductor package includes a semiconductor chip mounted on the base substrate. The semiconductor chip includes a core region disposed in a center part of the semiconductor chip, an internal circuit being provided in the core region. The semiconductor chip includes a plurality of IO cell regions disposed in a line along a side of the semiconductor chip, a differential circuit being provided in each of the plurality of IO cell regions. The semiconductor chip includes a non-inverting pad electrode disposed above each of the IO cell regions and electrically connected to a non-inverting terminal of the differential circuit. The semiconductor chip includes an inverting pad electrode disposed above each of the IO cell regions and connected to an inverting terminal of the differential circuit.
摘要翻译：驱动器半导体封装包括基底。半导体封装包括安装在基底基板上的半导体芯片。半导体芯片包括设置在半导体芯片的中心部分的芯区域，内部电路设置在芯区域中。半导体芯片包括沿着半导体芯片的一侧设置在一行中的多个IO单元区域，在多个IO单元区域的每一个中设置差分电路。半导体芯片包括设置在每个IO单元区域之上并且电连接到差分电路的非反相端子的非反相焊盘电极。半导体芯片包括设置在每个IO单元区域上方并连接到差分电路的反相端的反相焊盘电极。

2. 发明授权

US10218352B2 Semiconductor integrated circuit 有权
公开(公告)号：US10218352B2
公开(公告)日：2019-02-26
申请号：US15250857
申请日：2016-08-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shohei Fukuda
IPC分类号： H03K17/687 , H03K19/003 , H03K19/0175
摘要： A semiconductor integrated circuit includes an output circuit driven by a power voltage across a first and a second node. A control circuit is driven by the power voltage to control output a digital signal at a pad terminal, a logic value of the signal being set by a core circuit connected to the output circuit. The digital signal causes a voltage at the first node to be high and a voltage at the second node to low when a predetermined power voltage higher than a withstanding voltage of the output circuit is applied across the first and second nodes. The control circuit controls voltages across terminals of switching elements in the output circuit to be less than their withstanding voltages and to prevent current flowing from the pad terminal to the output circuit when the first power node is in a high impedance state.

3. 发明申请

US20160086935A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160086935A1
公开(公告)日：2016-03-24
申请号：US14643435
申请日：2015-03-10
申请人： Kabushiki Kaisha Toshiba
发明人： Shohei Fukuda
IPC分类号： H01L27/02
CPC分类号： H01L27/0251 , H01L27/0207 , H01L27/0285 , H01L27/0292 , H01L2224/05
摘要： According to one embodiment, a semiconductor device includes a first IO cell and a second IO cell arranged on a periphery of the core circuit. Each of the first IO cell and the second IO cell comprises: a power supply terminal to which a power supply voltage is applied; a ground terminal connected to ground; an RC delay circuit including a resistor having one terminal connected to one of the power supply terminal and the ground terminal and a capacitor having one terminal connected to the other terminal of the resistor and the other terminal connected to the other of the power supply terminal and the ground terminal; a P-type transistor; and an N-type transistor.
摘要翻译：根据一个实施例，半导体器件包括布置在核心电路的外围的第一IO单元和第二IO单元。第一IO单元和第二IO单元中的每一个包括：施加电源电压的电源端子; 接地端与地相连; RC延迟电路，其包括具有连接到所述电源端子和所述接地端子中的一个的一个端子的电阻器，以及电容器，所述电容器的一个端子连接到所述电阻器的另一端子，而另一个端子连接到所述电源端子的另一端子，地面终端; P型晶体管; 和N型晶体管。

4. 发明申请

US20150262964A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体芯片和半导体封装
公开(公告)号：US20150262964A1
公开(公告)日：2015-09-17
申请号：US14634571
申请日：2015-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Shohei Fukuda
IPC分类号： H01L23/00 , H01L23/528 , H01L23/48
CPC分类号： H01L24/49 , G06F17/5068 , H01L23/481 , H01L23/528 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/05554 , H01L2224/06133 , H01L2224/06135 , H01L2224/06139 , H01L2224/48011 , H01L2224/48091 , H01L2224/49431 , H01L2224/49433 , H01L2924/00014 , H01L2924/386 , H03K19/018514 , H03K19/17744 , H01L2224/45099 , H01L2224/05599
摘要： The driver semiconductor package includes a base substrate. The semiconductor package includes a semiconductor chip mounted on the base substrate. The semiconductor chip includes a core region disposed in a center part of the semiconductor chip, an internal circuit being provided in the core region. The semiconductor chip includes a plurality of IO cell regions disposed in a line along a side of the semiconductor chip, a differential circuit being provided in each of the plurality of IO cell regions. The semiconductor chip includes a non-inverting pad electrode disposed above each of the IO cell regions and electrically connected to a non-inverting terminal of the differential circuit. The semiconductor chip includes an inverting pad electrode disposed above each of the IO cell regions and connected to an inverting terminal of the differential circuit.
摘要翻译：驱动器半导体封装包括基底。半导体封装包括安装在基底基板上的半导体芯片。半导体芯片包括设置在半导体芯片的中心部分的芯区域，内部电路设置在芯区域中。半导体芯片包括沿着半导体芯片的一侧设置在一行中的多个IO单元区域，在多个IO单元区域的每一个中设置差分电路。半导体芯片包括设置在每个IO单元区域之上并且电连接到差分电路的非反相端子的非反相焊盘电极。半导体芯片包括设置在每个IO单元区域上方并连接到差分电路的反相端的反相焊盘电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式