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1. 发明申请

US20200091043A1 TERMINAL PLATE AND SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20200091043A1
公开(公告)日：2020-03-19
申请号：US16295741
申请日：2019-03-07
申请人： Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
发明人： Eitaro Miyake , Kazuya Kodani , Hiroshi Matsuyama , Tatsuya Hirakawa
IPC分类号： H01L23/492 , H01L25/07
摘要： Provided is a terminal plate according to an embodiment including: a first plate portion for being connected to a first semiconductor element; a second plate portion for being connected to a second semiconductor element; a third plate portion provided above the first plate portion and the second plate portion; a first connecting portion provided between the first plate portion and the third plate portion and connecting the first plate portion and the third plate portion; a second connecting portion provided between the second plate portion and the third plate portion and connecting the second plate portion and the third plate portion; a fourth plate portion provided above the first plate portion and the second plate portion and provided on the opposite side of the third plate portion with interposing the first and second plate portions; a third connecting portion provided between the first plate portion and the fourth plate portion and connecting the first plate portion and the fourth plate portion; a fourth connecting portion provided between the second plate portion and the fourth plate portion and connecting the second plate portion and the fourth plate portion; and a fifth plate portion provided above the fourth plate portion, the fifth plate portion connected to the fourth plate portion, and the fifth plate portion having a hole.

2. 发明申请

US20150076699A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150076699A1
公开(公告)日：2015-03-19
申请号：US14204203
申请日：2014-03-11
申请人： Kabushiki Kaisha Toshiba
发明人： Yo Sasaki , Yuuji Hisazato , Kazuya Kodani , Atsushi Yamamoto , Hitoshi Matsumura
IPC分类号： H01L23/48 , H01L23/00
CPC分类号： H01L23/481 , H01L24/04 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L2224/04026 , H01L2224/05655 , H01L2224/26152 , H01L2224/29109 , H01L2224/29111 , H01L2224/29118 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/3201 , H01L2224/32058 , H01L2224/32227 , H01L2224/32505 , H01L2224/82101 , H01L2224/83192 , H01L2224/83206 , H01L2224/83207 , H01L2224/83447 , H01L2224/83815 , H01L2924/01322 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/014 , H01L2924/01049 , H01L2924/0105 , H01L2924/00012
摘要： According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal.
摘要翻译：根据一个实施例，半导体器件包括半导体元件，互连层和接合层。互连层包括Cu。接合层包括在半导体元件和互连层之间的Cu和Cu之外的第一金属的合金的第一合金。第一合金的熔点高于第一金属的熔点。

3. 发明申请

US20150076516A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE 审中-公开
标题翻译：半导体器件和半导体器件
公开(公告)号：US20150076516A1
公开(公告)日：2015-03-19
申请号：US14202588
申请日：2014-03-10
申请人： Kabushiki Kaisha Toshiba
发明人： Yuuji Hisazato , Hiroki Sekiya , Yo Sasaki , Kazuya Kodani , Nobumitsu Tada , Hitoshi Matsumura , Tomohiro Iguchi
IPC分类号： H01L23/00
CPC分类号： H01L24/83 , H01L23/24 , H01L24/03 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/072 , H01L2224/0345 , H01L2224/03462 , H01L2224/04026 , H01L2224/05582 , H01L2224/05583 , H01L2224/05584 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/29111 , H01L2224/29139 , H01L2224/2929 , H01L2224/29294 , H01L2224/29339 , H01L2224/32013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2224/49175 , H01L2224/73265 , H01L2224/83447 , H01L2224/8346 , H01L2224/8384 , H01L2924/00014 , H01L2924/10272 , H01L2924/1033 , H01L2924/1305 , H01L2924/13055 , H01L2924/181 , H01L2924/3512 , H01L2924/35121 , H01L2924/01029 , H01L2924/0105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to one embodiment, a semiconductor device includes a semiconductor element and a metal film. The semiconductor element has a first surface and a second surface opposite to the first surface. The metal film is provided above the second surface of the semiconductor element. The metal film includes Cr.
摘要翻译：根据一个实施例，半导体器件包括半导体元件和金属膜。半导体元件具有与第一表面相对的第一表面和第二表面。金属膜设置在半导体元件的第二表面上方。金属膜包括Cr。

4. 发明授权

US08957522B2 Semiconductor device and manufacturing method of semiconductor device 有权
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US08957522B2
公开(公告)日：2015-02-17
申请号：US13787526
申请日：2013-03-06
申请人： Kabushiki Kaisha Toshiba
发明人： Yo Sasaki , Daisuke Hiratsuka , Atsushi Yamamoto , Kazuya Kodani , Yuuji Hisazato , Hitoshi Matsumura
IPC分类号： H01L23/52 , H01L23/532 , H01L21/768 , H01L21/58 , H01L23/00
CPC分类号： H01L23/53238 , H01L21/76841 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2224/2908 , H01L2224/29082 , H01L2224/29083 , H01L2224/29109 , H01L2224/29111 , H01L2224/29118 , H01L2224/29139 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/2917 , H01L2224/29171 , H01L2224/29172 , H01L2224/32225 , H01L2224/32503 , H01L2224/8381 , H01L2224/83815 , H01L2224/83825 , H01L2924/01322 , H01L2924/1301 , H01L2924/15747 , H01L2924/351 , H01L2924/00
摘要： According to one embodiment, the semiconductor device in the embodiment has an assembly substrate, a semiconductor chip, and a jointing layer. The semiconductor chip is joined to the assembly substrate via the jointing layer. An intervening diffusion barrier layer may be interposed between the chip and jointing layer. The jointing layer is an alloy layer mainly made of any metal selected from Sn, Zn and In or an alloy of Sn, Zn and In, and any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V or an alloy of any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V and any metal selected from Sn, Zn and In, where the alloy has a higher melting temperature than that of Sn, Zn and In or an alloy of Sn, Zn and/or In.
摘要翻译：根据一个实施例，本实施例中的半导体器件具有组装衬底，半导体芯片和接合层。半导体芯片通过接合层与组装衬底接合。可以在芯片和接合层之间插入介入的扩散阻挡层。接合层是主要由选自Sn，Zn和In的任何金属或Sn，Zn和In的合金以及选自Cu，Ni，Ag，Cr，Zr，Ti和V的任何金属或合金中的合金的合金层选自Cu，Ni，Ag，Cr，Zr，Ti和V中的任何金属以及选自Sn，Zn和In的任何金属，其中合金的熔化温度高于Sn，Zn和In，Sn或Sn的合金，Zn和/或In。

5. 发明授权

US10855196B2 Semiconductor device 有权
公开(公告)号：US10855196B2
公开(公告)日：2020-12-01
申请号：US16536921
申请日：2019-08-09
申请人： Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
发明人： Eitaro Miyake , Hiroshi Matsuyama , Tatsuya Hirakawa , Kazuya Kodani
IPC分类号： H02M7/00 , H05K7/14 , H01L23/00
摘要： A semiconductor device including a main board; a first board provided on the main board; first and second semiconductor elements provided on the first board; a first positive terminal provided on the first board; a first negative terminal provided on the first board; a first output terminal provided on the first board; a second board provided on the main board; third and fourth semiconductor elements provided on the second board; a second positive terminal provided on the second board; a second negative terminal provided on the second board; a second output terminal provided on the second board; a first terminal plate connecting the first positive terminal and the second positive terminal, a second terminal plate connecting the first negative terminal and the second negative terminal, and a third terminal plate connecting the first output terminal and the second output terminal.

6. 发明申请

US20160190032A1 WIRING BOARD AND SEMICONDUCTOR PACKAGE INCLUDING WIRING BOARD 审中-公开
标题翻译：接线板和半导体封装，包括接线板
公开(公告)号：US20160190032A1
公开(公告)日：2016-06-30
申请号：US14966577
申请日：2015-12-11
申请人： Kabushiki Kaisha Toshiba
发明人： Kazuya Kodani , Yuta Ichikura , Nobumitsu Tada , Hiroaki Ito , Toshiharu Ohbu , Taihei Koyama , Kazuaki Yuuki , Yosuke Nakazawa , Atsushi Yamamoto , Makoto Otani , Kazuhiro Ueda , Tomohiro Iguchi
IPC分类号： H01L23/367 , H05K1/03 , H05K1/09 , H01L23/31 , H01L23/498
CPC分类号： H01L23/367 , H01L23/3114 , H01L23/3731 , H01L23/473 , H01L23/49811 , H01L2924/0002 , H05K1/0306 , H05K1/09 , H05K2201/10166 , H01L2924/00
摘要： According to an embodiment, a wiring board includes an insulating board including a heat transfer region made of silicon nitride and having a thickness in a range between 0.2 mm and 1 mm; and a wiring layer including a pad stacked on the heat transfer region and made of a metal material having a thickness of 1.5 mm or more.
摘要翻译：根据实施例，布线板包括绝缘板，该绝缘板包括由氮化硅制成的厚度在0.2mm至1mm之间的传热区域; 以及布线层，其包括堆叠在传热区域上并由厚度为1.5mm以上的金属材料制成的焊盘。

7. 发明申请

US20160057881A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160057881A1
公开(公告)日：2016-02-25
申请号：US14626569
申请日：2015-02-19
申请人： Kabushiki Kaisha Toshiba
发明人： Nobumitsu Tada , Kazuya Kodani , Hiroaki Ito , Toshiharu Ohbu , Hitoshi Matsumura
IPC分类号： H05K7/02
CPC分类号： H05K7/1432 , H01L2224/40225
摘要： A semiconductor device includes a base plate, a semiconductor chip, and a first to a fourth terminal plates. The first terminal plate includes a first main body unit. The second terminal plate includes a second main body unit. The second main body unit opposes the first main body unit. The third terminal plate includes a third main body unit. The third main body unit opposes the first main body unit and the second main body unit. The fourth terminal plate includes a fourth main body unit. The fourth main body unit opposes the third main body unit. A thickness of the third main body unit is thinner than a thickness of the first main body unit. A thickness of the fourth main body unit is thinner than a thickness of the second main body unit.
摘要翻译：半导体器件包括基板，半导体芯片和第一至第四端子板。第一端子板包括第一主体单元。第二端子板包括第二主体单元。第二主体单元与第一主体单元相对。第三端子板包括第三主体单元。第三主体单元与第一主体单元和第二主体单元相对。第四端子板包括第四主体单元。第四主体单元与第三主体单元相反。第三主体单元的厚度比第一主体单元的厚度薄。第四主体单元的厚度比第二主体单元的厚度薄。

8. 发明授权

US09123704B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09123704B2
公开(公告)日：2015-09-01
申请号：US14204203
申请日：2014-03-11
申请人： Kabushiki Kaisha Toshiba
发明人： Yo Sasaki , Yuuji Hisazato , Kazuya Kodani , Atsushi Yamamoto , Hitoshi Matsumura
IPC分类号： H01L23/48 , H01L23/52 , H01L23/00
CPC分类号： H01L23/481 , H01L24/04 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L2224/04026 , H01L2224/05655 , H01L2224/26152 , H01L2224/29109 , H01L2224/29111 , H01L2224/29118 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/3201 , H01L2224/32058 , H01L2224/32227 , H01L2224/32505 , H01L2224/82101 , H01L2224/83192 , H01L2224/83206 , H01L2224/83207 , H01L2224/83447 , H01L2224/83815 , H01L2924/01322 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/014 , H01L2924/01049 , H01L2924/0105 , H01L2924/00012
摘要： According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal.
摘要翻译：根据一个实施例，半导体器件包括半导体元件，互连层和接合层。互连层包括Cu。接合层包括在半导体元件和互连层之间的Cu和Cu之外的第一金属的合金的第一合金。第一合金的熔点高于第一金属的熔点。

9. 发明授权

US10896867B2 Terminal plate and semiconductor device 有权
公开(公告)号：US10896867B2
公开(公告)日：2021-01-19
申请号：US16295741
申请日：2019-03-07
申请人： Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
发明人： Eitaro Miyake , Kazuya Kodani , Hiroshi Matsuyama , Tatsuya Hirakawa
IPC分类号： H01L23/492 , H01L25/07 , H01L23/498 , H01L23/52 , H01L23/64 , H01L23/367 , H01L23/538
摘要： Provided is a terminal plate according to an embodiment including: a first plate portion for being connected to a first semiconductor element; a second plate portion for being connected to a second semiconductor element; a third plate portion provided above the first plate portion and the second plate portion; a first connecting portion provided between the first plate portion and the third plate portion and connecting the first plate portion and the third plate portion; a second connecting portion provided between the second plate portion and the third plate portion and connecting the second plate portion and the third plate portion; a fourth plate portion provided above the first plate portion and the second plate portion and provided on the opposite side of the third plate portion with interposing the first and second plate portions; a third connecting portion provided between the first plate portion and the fourth plate portion and connecting the first plate portion and the fourth plate portion; a fourth connecting portion provided between the second plate portion and the fourth plate portion and connecting the second plate portion and the fourth plate portion; and a fifth plate portion provided above the fourth plate portion, the fifth plate portion connected to the fourth plate portion, and the fifth plate portion having a hole.

10. 发明授权

US09795049B2 Semiconductor device 有权
公开(公告)号：US09795049B2
公开(公告)日：2017-10-17
申请号：US14626569
申请日：2015-02-19
申请人： Kabushiki Kaisha Toshiba
发明人： Nobumitsu Tada , Kazuya Kodani , Hiroaki Ito , Toshiharu Ohbu , Hitoshi Matsumura
IPC分类号： H05K7/14
CPC分类号： H05K7/1432 , H01L2224/40225
摘要： A semiconductor device includes a base plate, a semiconductor chip, and a first to a fourth terminal plates. The first terminal plate includes a first main body unit. The second terminal plate includes a second main body unit. The second main body unit opposes the first main body unit. The third terminal plate includes a third main body unit. The third main body unit opposes the first main body unit and the second main body unit. The fourth terminal plate includes a fourth main body unit. The fourth main body unit opposes the third main body unit. A thickness of the third main body unit is thinner than a thickness of the first main body unit. A thickness of the fourth main body unit is thinner than a thickness of the second main body unit.

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