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1. 发明授权

US11563090B2 Semiconductor device 有权
公开(公告)号：US11563090B2
公开(公告)日：2023-01-24
申请号：US17014032
申请日：2020-09-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Johji Nishio , Tatsuo Shimizu
IPC分类号： H01L29/16 , H01L29/66 , H01L29/78 , H01L29/04 , H01L29/872 , H01L29/06 , H01L29/739
摘要： According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.

2. 发明授权

US11469301B2 Semiconductor device, semiconductor device manufacturing method, inverter circuit, driver device, vehicle, and elevator 有权
公开(公告)号：US11469301B2
公开(公告)日：2022-10-11
申请号：US17176525
申请日：2021-02-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tatsuo Shimizu , Yukio Nakabayashi , Johji Nishio , Chiharu Ota , Toshihide Ito
IPC分类号： H01L29/10 , H01L29/16 , H01L29/78 , H01L21/04 , H01L29/66 , B66B11/04 , B61C3/00 , B61C17/00 , B60K1/00 , B60L53/20 , H02P27/06
摘要： This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm−3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm−3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm−3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm−3.

3. 发明授权

US11239079B2 Semiconductor device, method for manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator 有权
公开(公告)号：US11239079B2
公开(公告)日：2022-02-01
申请号：US17000572
申请日：2020-08-24
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tatsuo Shimizu , Yukio Nakabayashi , Johji Nishio , Chiharu Ota , Toshihide Ito
IPC分类号： H01L29/16 , H01L21/04 , H01L29/06 , H01L29/10 , H01L29/51 , H01L29/78 , H01L21/02 , H01L29/66 , H02P27/06 , B61C3/00 , B60L50/51 , B66B11/04
摘要： A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm−3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm−3 and a carbon concentration at the first position is equal to or less than 1×1018 cm3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm−3.

4. 发明授权

US10930732B2 Semiconductor device including a silicon carbide layer 有权
公开(公告)号：US10930732B2
公开(公告)日：2021-02-23
申请号：US16861317
申请日：2020-04-29
申请人： Kabushiki Kaisha Toshiba
发明人： Johji Nishio , Mitsuhiro Kushibe , Tatsuo Shimizu
IPC分类号： H01L29/06 , H01L29/868 , H01L29/16 , H01L29/66 , H01L29/739 , H01L29/32 , H01L29/861 , H01L21/265 , H01L21/04 , H01L29/04
摘要： A semiconductor device of the embodiment includes: a first region provided in a silicon carbide layer; and a second region provided around the first region in the silicon carbide layer, the second region having a higher concentration of at least one kind of a lifetime killer impurity selected from the group consisting of B (boron), Ti (titanium), V (vanadium), He (helium) and H+ (proton) than a concentration of a lifetime killer impurity in the first region.

5. 发明授权

US10529558B2 Semiconductor device, substrate, method for manufacturing semiconductor device, and method for manufacturing substrate 有权
公开(公告)号：US10529558B2
公开(公告)日：2020-01-07
申请号：US16055300
申请日：2018-08-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Johji Nishio , Tatsuo Shimizu , Mitsuhiro Kushibe
IPC分类号： H01L21/02 , H01L29/16 , H01L21/04
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region including a first compound including silicon and carbon, and a second semiconductor region including a second compound including silicon and carbon. The first semiconductor region includes first to third regions contacting the second semiconductor region. The third region is positioned between the first region and the second region. The first region and the second region include germanium. The third region does not include germanium, or a concentration of germanium in the third region is lower than a concentration of germanium in the first region and lower than a concentration of germanium in the second region.

6. 发明申请

US20160268381A1 SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体衬底，半导体器件及制造半导体器件的方法
公开(公告)号：US20160268381A1
公开(公告)日：2016-09-15
申请号：US15055707
申请日：2016-02-29
申请人： Kabushiki Kaisha Toshiba
发明人： Chiharu OTA , Johji Nishio , Kazuto Takao
IPC分类号： H01L29/16 , C30B29/36 , H01L21/02 , H01L29/04 , H01L29/34
CPC分类号： H01L29/1608 , C30B29/36 , H01L21/02378 , H01L21/02447 , H01L21/02529 , H01L21/02609 , H01L29/045 , H01L29/32 , H01L29/34 , H01L29/36 , H01L29/7393 , H01L29/868
摘要： A semiconductor substrate of an embodiment includes a SiC layer having a surface inclined in a direction plus or minus 5° from a {0001} face at an off angle of 0° to 10°. Area density of threading edge dislocation clusters in the SiC layer is 18.8 cm−2 or less, each of the threading edge dislocation clusters includes a plurality of threading edge dislocations on the surface, the threading edge dislocations included in each of the threading edge dislocation clusters exist in a region that extends in a [1-100] direction plus or minus 5° and has a width of 30 μm or less, each of the threading edge dislocation clusters includes at least three threading edge dislocations adjacent at an interval of 30 μm or less, and an interval of adjacent threading edge dislocations in each of the threading edge dislocation clusters is 70 μm or less.
摘要翻译：实施方式的半导体衬底包括具有从0°至10°的偏离角从{0001}面向零±5°倾斜的表面的SiC层。 SiC层中的穿线边缘位错簇的面积密度为18.8cm -2以下，每个穿线边缘位错簇包括表面上的多个穿线边缘位错，每个穿线边缘位错簇中包括的穿线边缘位错存在于[1-100]方向上加或减5°并且具有30μm以下的宽度的区域中，每个穿线边缘位错簇包括以30μm的间隔相邻的至少三个穿透边缘位错并且每个穿线边缘位错簇中的相邻穿线边缘位错的间隔为70μm以下。

7. 发明授权

US09099342B2 Transistor and method for manufacturing same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US09099342B2
公开(公告)日：2015-08-04
申请号：US14661158
申请日：2015-03-18
申请人： Kabushiki Kaisha Toshiba
发明人： Johji Nishio , Hiroshi Kono , Takuma Suzuki , Tatsuo Shimizu , Takashi Shinohe
IPC分类号： H01L21/336 , H01L29/10 , H01L29/66
CPC分类号： H01L29/105 , H01L29/045 , H01L29/0878 , H01L29/1041 , H01L29/1095 , H01L29/1608 , H01L29/161 , H01L29/66068 , H01L29/7395 , H01L29/7802
摘要： According to one embodiment, a transistor includes: a structural body; an insulating film; a control electrode; a first electrode; and a second electrode. The structural body includes a first through a third semiconductor regions, and includes a compound semiconductor having a first and a second elements. The first electrode is electrically continuous with the third semiconductor region. The second electrode is electrically continuous with the first semiconductor region. The structural body has a first region provided above a lower end of the second semiconductor region and a second region other than the first region. The first region is a region formed by making a ratio of concentration of source gas of the second element to concentration of source gas of the first element larger than 1.0. Impurity concentration of the first conductivity type in the first region is higher than that in the second region.
摘要翻译：根据一个实施例，晶体管包括：结构体; 绝缘膜; 控制电极; 第一电极; 和第二电极。结构体包括第一至第三半导体区域，并且包括具有第一和第二元素的化合物半导体。第一电极与第三半导体区域电连接。第二电极与第一半导体区域电连接。结构体具有设置在第二半导体区域的下端上方的第一区域和除第一区域之外的第二区域。第一区域是通过使第二元素的源气体的浓度与第一元素的源气体的浓度比大于1.0而形成的区域。第一区域的第一导电类型的杂质浓度高于第二区域。

8. 发明申请

US20150060884A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150060884A1
公开(公告)日：2015-03-05
申请号：US14467146
申请日：2014-08-25
申请人： Kabushiki Kaisha Toshiba
发明人： Chiharu OTA , Tatsuo Shimizu , Johji Nishio , Takashi Shinohe
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/0634 , H01L29/045 , H01L29/0619 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/167 , H01L29/36 , H01L29/6606 , H01L29/7395 , H01L29/7802 , H01L29/7816 , H01L29/8613 , H01L29/872
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a first electrode. The first semiconductor region is of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, and is of a second conductivity type. The third semiconductor region is provided on the second semiconductor region, and is of the second conductivity type. The third semiconductor region contains a first impurity of the first conductivity type and a second impurity of the second conductivity type, and satisfies 1
摘要翻译：根据一个实施例，半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域和第一电极。第一半导体区域是第一导电类型。第二半导体区域设置在第一半导体区域上，并且是第二导电类型。第三半导体区域设置在第二半导体区域上，并且是第二导电类型。第三半导体区域包含第一导电类型的第一杂质和第二导电类型的第二杂质，并且满足1

9. 发明授权

US08951898B2 Method for manufacturing a silicon carbide DIMOSFET 有权
标题翻译：制造碳化硅DIMOSFET的方法
公开(公告)号：US08951898B2
公开(公告)日：2015-02-10
申请号：US14172059
申请日：2014-02-04
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroshi Kono , Takashi Shinohe , Takuma Suzuki , Johji Nishio
IPC分类号： H01L21/265 , H01L21/04 , H01L29/66 , H01L29/16 , H01L29/739 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L21/0465 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66477 , H01L29/7395 , H01L29/7802 , H01L29/7827
摘要： According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration.
摘要翻译：根据一个实施例，半导体器件包括第一，第二，第三，第四和第五半导体区域，绝缘膜，控制电极以及第一和第二电极。第一，第二，第三，第四和第五半导体区域包括碳化硅。第一半导体区域具有第一杂质浓度，并具有第一部分。第二半导体区域设置在第一半导体区域上。第三半导体区域设置在第二半导体区域上。第四半导体区域设置在第一部分和第二半导体区域之间。第四半导体区域设置在第一部分和第三半导体区域之间。第五半导体区域包括设置在第一部分和第二半导体区域之间的第一区域，并且具有高于第一杂质浓度的第二杂质浓度。

10. 发明申请

US20140284621A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140284621A1
公开(公告)日：2014-09-25
申请号：US14205887
申请日：2014-03-12
申请人： Kabushiki Kaisha Toshiba
发明人： Tatsuo SHIMIZU , Johji Nishio , Chiharu Ota , Takashi Shinohe
IPC分类号： H01L29/16 , H01L21/04
CPC分类号： H01L29/1608 , C30B29/36 , H01L21/046 , H01L21/0465 , H01L21/049 , H01L29/0847 , H01L29/167 , H01L29/66068 , H01L29/66333 , H01L29/7395 , H01L29/7802 , H01L29/7827
摘要： A semiconductor device of an embodiment includes an n-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element A to the concentration of the element D in the above combination is higher than 0.40 but lower than 0.95, and the concentration of the element D forming the above combination is not lower than 1×1018 cm−3 and not higher than 1×1022 cm−3.
摘要翻译：实施例的半导体器件包括含有p型杂质和n型杂质的n型SiC杂质区。当p型杂质是元素A，n型杂质是元素D时，元素A和元素D形成Al（铝），Ga（镓）或In（铟）和N（氮）和/或B（硼）和P（磷）的组合。元素A的浓度与上述组合中的元素D的浓度的比例高于0.40但低于0.95，构成上述组合的元素D的浓度不低于1×1018cm-3 不高于1×1022cm-3。

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