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1. 发明授权

US09305637B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09305637B2
公开(公告)日：2016-04-05
申请号：US14194781
申请日：2014-03-02
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Rieko Funatsuki , Takuya Futatsuyama , Fumitaka Arai
IPC分类号： G11C11/34 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3431 , G11C16/3459
摘要： A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation.
摘要翻译：非易失性半导体存储器件包括具有非易失性存储器单元的存储单元阵列，其中多个值中的一个可通过设置多个阈值中的一个来编程，以及对存储单元执行写入操作的控制电路。由控制电路执行的写入操作包括用于确定擦除状态下的存储单元的阈值电平的预编程验证操作，以及基于从多个编程电压选择编程电压的编程操作预编程验证操作的确定结果。

2. 发明申请

US20160322373A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20160322373A1
公开(公告)日：2016-11-03
申请号：US15205954
申请日：2016-07-08
申请人： Kabushiki Kaisha Toshiba
发明人： Wataru SAKAMOTO , Ryota Suzuki , Tatsuya Okamoto , Tatsuya Kato , Fumitaka Arai
IPC分类号： H01L27/115 , G11C16/24 , G11C16/30 , G11C16/04 , H01L29/06 , H01L23/528
CPC分类号： H01L27/11556 , G11C16/0408 , G11C16/0483 , H01L23/528 , H01L27/11519 , H01L27/11582 , H01L29/0649 , H01L29/66825 , H01L29/7926
摘要： A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
摘要翻译：半导体存储器件包括两个第一电极膜，第一列和第二绝缘膜。两个第一电极膜沿第一方向延伸并且在第二方向上彼此分离。第一列设置在两个第一电极膜之间，并且具有多个第一构件和多个绝缘构件。第一构件和每个绝缘构件中的每一个在第一方向上交替布置。多个第一构件中的一个具有设置在半导体柱和第二电极膜之间的半导体柱，第二电极膜和第一绝缘膜。半导体柱，第一绝缘膜和第二电极膜沿第二方向排列。第二绝缘膜设置在第一列和两个第一电极膜之一之间。

3. 发明授权

US09450181B2 Semiconductor memory and method of manufacturing the same 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US09450181B2
公开(公告)日：2016-09-20
申请号：US14288321
申请日：2014-05-27
申请人： Kabushiki Kaisha Toshiba
发明人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
IPC分类号： H01L29/02 , H01L45/00 , H01L27/105 , H01L27/115 , H01L27/24
CPC分类号： H01L27/249 , H01L21/02532 , H01L21/02595 , H01L21/28282 , H01L21/30604 , H01L21/31055 , H01L21/3212 , H01L21/32136 , H01L21/762 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L29/513 , H01L29/518 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
摘要翻译：半导体存储器包括通过在垂直于衬底的方向上堆叠平行于衬底延伸的多个层而形成的多个条状有源区域，形成在有源区域的第一侧表面上的第一栅极电极，第一栅极电极侧表面垂直于衬底，形成在有源区的第二侧表面上的第二栅电极，第二侧表面垂直于衬底。这些层彼此自对准地构图，有源区和第一栅电极的交点形成多个存储单元，并且交叉平面中的多个存储单元共享第一栅电极。

4. 发明授权

US09257443B1 Memory device and method for manufacturing the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US09257443B1
公开(公告)日：2016-02-09
申请号：US14598726
申请日：2015-01-16
申请人： Kabushiki Kaisha Toshiba
发明人： Fumie Kikushima , Tatsuya Kato , Wataru Sakamoto , Fumitaka Arai
IPC分类号： H01L27/115 , H01L23/528 , H01L23/532 , H01L29/423 , H01L29/49 , H01L21/02 , H01L21/28 , H01L29/788
CPC分类号： H01L27/11556 , H01L21/0217 , H01L21/28273 , H01L29/7883
摘要： According to an embodiment, a semiconductor memory device includes a semiconductor pillar, a first electrode film, a second electrode film, a first insulating film, a second insulating film, and a wiring film. The semiconductor member is extending in a first direction. The first electrode film is disposed at the lateral side of the semiconductor member away from the semiconductor member. The second electrode film is provided between the semiconductor member and the first electrode film. The first insulating film is provided between the semiconductor member and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode film. The wiring film is disposed in a wiring lead-out region adjacent to the memory cell region. And the first electrode film is formed of a material different from a material of the wiring film, and being electrically connected to the wiring film.
摘要翻译：根据实施例，半导体存储器件包括半导体柱，第一电极膜，第二电极膜，第一绝缘膜，第二绝缘膜和布线膜。半导体部件沿第一方向延伸。第一电极膜设置在半导体部件的横向侧远离半导体部件。第二电极膜设置在半导体部件和第一电极膜之间。第一绝缘膜设置在半导体部件和第二电极膜之间。第二绝缘膜设置在第二电极膜和第一电极膜之间。布线膜设置在与存储单元区域相邻的布线引出区域中。并且第一电极膜由与布线膜的材料不同的材料形成，并且与布线膜电连接。

5. 发明授权

US09735167B2 Semiconductor memory device and method for manufacturing the same 有权
公开(公告)号：US09735167B2
公开(公告)日：2017-08-15
申请号：US14840345
申请日：2015-08-31
申请人： Kabushiki Kaisha Toshiba
发明人： Tatsuya Kato , Fumitaka Arai , Satoshi Nagashima , Katsuyuki Sekine , Yuta Watanabe , Keisuke Kikutani , Atsushi Murakoshi
IPC分类号： H01L27/11529 , H01L27/11556 , H01L23/528 , H01L27/11548 , H01L23/522 , H01L27/11521 , H01L27/11517 , H01L27/11578 , H01L27/1157 , H01L27/11568 , H01L21/768 , H01L27/11573 , H01L27/11524 , H01L27/24 , H01L27/105 , H01L27/11551
CPC分类号： H01L27/11556 , H01L21/76885 , H01L23/5226 , H01L23/528 , H01L27/1052 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11548 , H01L27/11551 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11578 , H01L27/2481 , H01L29/7889
摘要： A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a second direction crossing the first direction, a plurality of semiconductor pillars arrayed in a row along the first direction in each of spaces among the first interconnects and extending in a third direction crossing the first direction and the second direction, a first electrode disposed between one of the semiconductor pillars and one of the first interconnects, a first insulating film disposed between the first electrode and one of the first interconnects, a first insulating member disposed between the semiconductor pillars in the first direction and extending in the third direction and opposed the first interconnects not via the first insulating film.

6. 发明授权

US09431412B1 Semiconductor memory device and method for manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09431412B1
公开(公告)日：2016-08-30
申请号：US14847921
申请日：2015-09-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tatsuya Kato , Fumitaka Arai , Satoshi Nagashima , Katsuyuki Sekine , Yuta Watanabe , Keisuke Kikutani , Atsushi Murakoshi
IPC分类号： H01L21/336 , H01L27/115
CPC分类号： H01L27/11556 , H01L27/11521 , H01L27/11524
摘要： According to one embodiment, a semiconductor memory device includes a first array extending in a first direction, a second array extending in the first direction, and a second electrode film. The second array is arranged with the first array in a second direction crossing the first direction. The second electrode film provided between the first array and the second array. The second electrode film extends in the first direction. Each of the first array and the second array include a first structure, a second structure arranged in the first direction, a fourth insulating film provided between the first structure and the second structure, and a third insulating film provided between the first structure and the second electrode film, provided also between the first structure and the fourth insulating film.
摘要翻译：根据一个实施例，半导体存储器件包括沿第一方向延伸的第一阵列，在第一方向上延伸的第二阵列和第二电极膜。第二阵列以与第一方向交叉的第二方向布置有第一阵列。设置在第一阵列和第二阵列之间的第二电极膜。第二电极膜沿第一方向延伸。第一阵列和第二阵列中的每一个包括第一结构，沿第一方向布置的第二结构，设置在第一结构和第二结构之间的第四绝缘膜，以及设置在第一结构和第二结构之间的第三绝缘膜电极膜，也设置在第一结构体和第四绝缘膜之间。

7. 发明申请

US20130248978A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130248978A1
公开(公告)日：2013-09-26
申请号：US13837246
申请日：2013-03-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takeshi SAKAGUCHI , Fumitaka Arai
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , H01L27/11524
摘要： According to an embodiment, a semiconductor device includes a plurality of first semiconductor regions that extend in a first direction and are arranged in a direction intersecting the first direction, and each element separation region that is provided between the plurality of first semiconductor regions. The element separation region includes a first element separation portion that is formed to a first depth from an upper surface of the first semiconductor region and a second element separation portion that is formed from the first depth to a second depth more than the first depth and electrically insulates between adjacent elements.
摘要翻译：根据实施例，半导体器件包括多个第一半导体区域，其沿第一方向延伸并且沿与第一方向相交的方向布置，并且每个元件分离区域设置在多个第一半导体区域之间。元件分离区包括从第一半导体区域的上表面形成为第一深度的第一元件分离部分和从第一深度到第二深度大于第一深度而形成的第二元素分离部分，在相邻元件之间绝缘。

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